公开(公告)号：US08922263B2

公开(公告)日：2014-12-30

申请号：US12541358

申请日：2009-08-14

申请人： Hiroshi Kamizuma ,  Taizo Yamawaki ,  Yukinori Akamine ,  Koji Maeda

发明人： Hiroshi Kamizuma ,  Taizo Yamawaki ,  Yukinori Akamine ,  Koji Maeda

IPC分类号： G11C5/14 ,  H03K19/003 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/094 ,  H03L7/00 ,  H03K3/00 ,  G06F13/42 ,  H04W52/02

CPC分类号： G06F1/3296 ,  G06F1/12 ,  G06F13/4243 ,  H04W52/0274 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D70/00 ,  Y02D70/1224

摘要： The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

摘要翻译： 在输入接口处减少选择适合于抽样有效载荷数据的时钟信号的相位的数据采样单元的功耗。 半导体集成电路包括输入接口和内部核心电路。 输入接口包括滞后电路和数据采样单元。 滞后电路将第一和第二输入阈值之间的输入信号作为睡眠命令检测。 数据采样单元根据同步信号选择采样时钟信号的适当相位，并采样有效载荷数据。 当检测到睡眠命令时，还向内部核心电路和数据采样单元提供睡眠信号，并将它们控制为低功耗状态。

公开(公告)号：US20080113625A1

公开(公告)日：2008-05-15

申请号：US11940733

申请日：2007-11-15

申请人： Koji Maeda ,  Satoshi Tanaka ,  Taizo Yamawaki ,  Yukinori Akamine ,  Masahiro Ito

发明人： Koji Maeda ,  Satoshi Tanaka ,  Taizo Yamawaki ,  Yukinori Akamine ,  Masahiro Ito

IPC分类号： H04B17/00

CPC分类号： H04B1/30

摘要： When generating an RF test signal for mismatch calibration for receiver in order to calibrate reception mismatch of an I-phase signal and a Q-phase signal that are output from demodulated signal processing circuits coupled to mixers for receiving, a Tx VCO avoids covering the higher frequency of an RF received signal in an FDD system. An RF test signal generating unit generates, in a calibration mode of a mismatch calibration for receiver circuit, the RF test signal by using an oscillation output signal of the Tx VCO and other circuits, and supplies the same to the mixers for receiving via a switch. The RF test signal has a frequency within an RF reception frequency band that is higher than that of an RF transmission signal with the maximum frequency band of multiband radio frequency communications. By switching the switch in a reception mode, an output of a low-noise amplifier that amplifies the RF received signal received by an antenna is supplied to each of the mixers for receiving.

摘要翻译： 为了校准从耦合到混频器进行接收的解调信号处理电路输出的I相信号和Q相信号的接收不匹配，为接收机生成用于失配校准的RF测试信号时，Tx VCO避免覆盖较高的 FDD系统中RF接收信号的频率。 RF测试信号产生单元通过使用Tx VCO和其它电路的振荡输出信号在接收机电路的不匹配校准的校准模式中产生RF测试信号，并将其提供给用于经由开关接收的混频器 。 RF测试信号具有比具有多频带无线电频率通信的最大频带的RF传输信号的RF接收频带内的频率。 通过在接收模式下切换开关，将放大天线接收到的RF接收信号的低噪声放大器的输出提供给每个混频器进行接收。

公开(公告)号：US07996003B2

公开(公告)日：2011-08-09

申请号：US11940733

申请日：2007-11-15

申请人： Koji Maeda ,  Satoshi Tanaka ,  Taizo Yamawaki ,  Yukinori Akamine ,  Masahiro Ito

发明人： Koji Maeda ,  Satoshi Tanaka ,  Taizo Yamawaki ,  Yukinori Akamine ,  Masahiro Ito

IPC分类号： H04W24/00 ,  H04B17/00

CPC分类号： H04B1/30

摘要： When generating an RF test signal for mismatch calibration for receiver in order to calibrate reception mismatch of an I-phase signal and a Q-phase signal that are output from demodulated signal processing circuits coupled to mixers for receiving, a Tx VCO avoids covering the higher frequency of an RF received signal in an FDD system. An RF test signal generating unit generates, in a calibration mode of a mismatch calibration for receiver circuit, the RF test signal by using an oscillation output signal of the Tx VCO and other circuits, and supplies the same to the mixers for receiving via a switch. The RF test signal has a frequency within an RF reception frequency band that is higher than that of an RF transmission signal with the maximum frequency band of multiband radio frequency communications. By switching the switch in a reception mode, an output of a low-noise amplifier that amplifies the RF received signal received by an antenna is supplied to each of the mixers for receiving.

摘要翻译： 为了校准从耦合到混频器进行接收的解调信号处理电路输出的I相信号和Q相信号的接收不匹配，为接收机生成用于失配校准的RF测试信号时，Tx VCO避免覆盖较高的 FDD系统中RF接收信号的频率。 RF测试信号产生单元通过使用Tx VCO和其它电路的振荡输出信号在接收机电路的不匹配校准的校准模式中产生RF测试信号，并将其提供给用于经由开关接收的混频器 。 RF测试信号具有比具有多频带无线电频率通信的最大频带的RF传输信号的RF接收频带内的频率。 通过在接收模式下切换开关，将放大天线接收到的RF接收信号的低噪声放大器的输出提供给每个混频器进行接收。

公开(公告)号：US08411730B2

公开(公告)日：2013-04-02

申请号：US12955865

申请日：2010-11-29

申请人： Koji Maeda ,  Taizo Yamawaki ,  Yukinori Akamine

发明人： Koji Maeda ,  Taizo Yamawaki ,  Yukinori Akamine

IPC分类号： H04B1/38

CPC分类号： H04L27/3863 ,  H04B17/0085 ,  H04B17/21 ,  H04L25/06

摘要： The semiconductor integrated communication circuit includes:a low-noise amplifier; a receive mixer; a receive VCO; a demodulation-processing circuit; a modulation-processing circuit; a transmit mixer; a transmit VCO; a second-order-distortion-characteristic-calibration circuit; a quadrature-receive-signal-calibration circuit; and a test-signal generator. The test-signal generator generates first and second test signals using the transmit VCO. In the second-order-distortion-characteristic-calibration mode, the second-order-distortion-characteristic-calibration circuit variably changes an operation parameter of the receive mixer thereby to calibrate the second-order distortion characteristic to achieve its best condition while the first test signal is supplied to the receive mixer. In the quadrature-receive-signal-calibration mode, the quadrature-receive-signal-calibration circuit calibrates IQ mismatch of a quadrature receive signal to achieve the best condition thereof while the second test signal is supplied to the receive mixer. The integrated communication circuit can minimize the increase in chip footprint of a test-signal-generating circuit used to perform calibrations of both the second-order characteristic and IQ mismatch.

摘要翻译： 半导体集成通信电路包括：低噪声放大器; 接收混音器 接收VCO; 解调处理电路; 调制处理电路; 发射混频器; 发射VCO; 二阶畸变特征校准电路; 正交接收信号校准电路; 和测试信号发生器。 测试信号发生器使用发射VCO产生第一和第二测试信号。 在二次失真特性校准模式中，二阶失真特性校准电路可变地改变接收混频器的操作参数，从而校正二阶失真特性，以实现其最佳状态，而第一 测试信号被提供给接收混频器。 在正交接收信号校准模式中，正交接收信号校准电路校准正交接收信号的IQ失配，以实现其最佳状态，同时将第二测试信号提供给接收混频器。 集成通信电路可以最小化用于执行二阶特性和IQ失配校准的测试信号发生电路的芯片占用面积的增加。

公开(公告)号：US08442461B2

公开(公告)日：2013-05-14

申请号：US12854216

申请日：2010-08-11

申请人： Takayasu Norimatsu ,  Taizo Yamawaki ,  Yukinori Akamine ,  Koji Maeda

发明人： Takayasu Norimatsu ,  Taizo Yamawaki ,  Yukinori Akamine ,  Koji Maeda

IPC分类号： H03C1/62 ,  H04B17/00

CPC分类号： H04B1/0483 ,  H03C5/00 ,  H04B2001/0491

摘要： The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.

摘要翻译： 发射机合成幅度和相位分量，并以高精度高速校准振幅和相位分量之间的延迟失配。 发射机具有：幅度信号路径中的数模转换器（DAC）和低通滤波器（LPF）; 以及相位调制器，其可操作以将相位分量转换成其相位信号路径中的RF分量。 在延迟校准的操作中，将测试输入信号提供给幅度信号路径中的延迟校准单元，并且延迟校准单元向DAC提供测试输入信号。 然后，LPF产生测试输出信号。 延迟校准单元检测测试输出信号相对于测试输入信号的延迟，校准从延迟校准单元的输入到LPF的输出的范围内的幅度信号延迟，减小幅度和相位之间的差异 相位调制器在相位信号路径中的信号延迟。

公开(公告)号：US20110128992A1

公开(公告)日：2011-06-02

申请号：US12955865

申请日：2010-11-29

申请人： Koji MAEDA ,  Taizo Yamawaki ,  Yukinori Akamine

发明人： Koji MAEDA ,  Taizo Yamawaki ,  Yukinori Akamine

IPC分类号： H04L27/18 ,  H04B7/00 ,  H04B1/69 ,  H04B17/00

CPC分类号： H04L27/3863 ,  H04B17/0085 ,  H04B17/21 ,  H04L25/06

摘要： The semiconductor integrated communication circuit includes:a low-noise amplifier; a receive mixer; a receive VCO; a demodulation-processing circuit; a modulation-processing circuit; a transmit mixer; a transmit VCO; a second-order-distortion-characteristic-calibration circuit; a quadrature-receive-signal-calibration circuit; and a test-signal generator. The test-signal generator generates first and second test signals using the transmit VCO. In the second-order-distortion-characteristic-calibration mode, the second-order-distortion-characteristic-calibration circuit variably changes an operation parameter of the receive mixer thereby to calibrate the second-order distortion characteristic to achieve its best condition while the first test signal is supplied to the receive mixer. In the quadrature-receive-signal-calibration mode, the quadrature-receive-signal-calibration circuit calibrates IQ mismatch of a quadrature receive signal to achieve the best condition thereof while the second test signal is supplied to the receive mixer. The integrated communication circuit can minimize the increase in chip footprint of a test-signal-generating circuit used to perform calibrations of both the second-order characteristic and IQ mismatch.

摘要翻译： 半导体集成通信电路包括：低噪声放大器; 接收混音器 接收VCO; 解调处理电路; 调制处理电路; 发射混频器; 发射VCO; 二阶畸变特征校准电路; 正交接收信号校准电路; 和测试信号发生器。 测试信号发生器使用发射VCO产生第一和第二测试信号。 在二次失真特性校准模式中，二阶失真特性校准电路可变地改变接收混频器的操作参数，从而校正二阶失真特性，以实现其最佳状态，而第一 测试信号被提供给接收混频器。 在正交接收信号校准模式中，正交接收信号校准电路校准正交接收信号的IQ失配，以实现其最佳状态，同时将第二测试信号提供给接收混频器。 集成通信电路可以最小化用于执行二阶特性和IQ失配校准的测试信号发生电路的芯片占用面积的增加。

公开(公告)号：US07346325B2

公开(公告)日：2008-03-18

申请号：US11179553

申请日：2005-07-13

申请人： Koji Maeda ,  Satoshi Tanaka ,  Irei Kyu ,  Yukinori Akamine ,  Manabu Kawabe

发明人： Koji Maeda ,  Satoshi Tanaka ,  Irei Kyu ,  Yukinori Akamine ,  Manabu Kawabe

IPC分类号： H04B1/10

CPC分类号： H04B1/30

摘要： This invention provides a receiver in which the calibration time by repeated operations to correct phase mismatch and amplitude mismatch between I and Q signals can be reduced. The receiver comprises mixers which convert received RF signals into quadrature modulated IF signals, signal paths which filter and amplify and output the quadrature modulated signals output from the mixers, a calibration circuit which calibrates phase and amplitude mismatches between the I and Q components of the quadrature modulated signals output through the signal paths, a frequency converter which, when the mixers or the signal paths selected output calibration signals with IF frequency instead of the quadrature modulated signals, converts the calibration signals into those with a frequency higher than IF frequency, and an arithmetic operation circuit which calculates phase and amplitude mismatches from the calibration signals output by the frequency converter and outputs calculation results. The calibration circuit executes calibration, using the calculation results.

摘要翻译： 本发明提供一种接收机，其中通过重复操作来校正I和Q信号之间的相位失配和幅度失配的校准时间可以减少。 该接收机包括将接收的RF信号转换为正交调制的IF信号的混频器，对从混频器输出的正交调制信号进行滤波和放大并输出的信号路径;校准电路，其校准正交的I和Q分量之间的相位和幅度失配 调制信号通过信号路径输出，频率转换器，当混频器或信号路径选择输出具有IF频率而不是正交调制信号的校准信号时，将校准信号转换为频率高于IF频率的校准信号， 算术运算电路，从由变频器输出的校准信号计算相位和幅度失配，并输出计算结果。 校准电路使用计算结果执行校准。

公开(公告)号：US20060189286A1

公开(公告)日：2006-08-24

申请号：US11337590

申请日：2006-01-24

申请人： Irei Kyu ,  Satoshi Tanaka ,  Koji Maeda ,  Yukinori Akamine

发明人： Irei Kyu ,  Satoshi Tanaka ,  Koji Maeda ,  Yukinori Akamine

IPC分类号： H04B7/00 ,  H04B7/08 ,  H03D5/00 ,  H04B1/06

CPC分类号： H03F3/1935 ,  H03F3/19 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H04B1/0053 ,  H04B1/0458

摘要： A multi-band radio module for selectively supplying received signals in a plurality of frequency bands to a low noise amplifier via an input impedance matching circuit by switching over the operation mode of the low noise amplifier is comprised of: a pre-stage amplification unit including a plurality of fundamental amplifiers connected to one another in parallel, the fundamental amplifiers sharing a load impedance connected to a source voltage and a grounded degeneration impedance and having input signal lines commonly connected to an input impedance matching circuit; a post-stage amplifier to which the output signals of the plurality of fundamental amplifiers are commonly inputted; and a bias control unit for selectively turning on the fundamental amplifiers, wherein the input impedance of the low noise amplifier is selectively optimized for the matching circuit depending on the RF band to be received.

摘要翻译： 一种用于通过切换低噪声放大器的操作模式通过输入阻抗匹配电路将多个频带中的接收信号选择性地提供给低噪声放大器的多频带无线电模块包括：前级放大单元，包括 基本放大器并联连接的多个基本放大器，所述基本放大器共享与源极电压和接地退化阻抗相连的负载阻抗，并且具有共同连接到输入阻抗匹配电路的输入信号线; 共同输入多个基本放大器的输出信号的后级放大器; 以及用于选择性地接通基本放大器的偏置控制单元，其中根据待接收的RF频带，选择性地优化低噪声放大器的输入阻抗，用于匹配电路。

公开(公告)号：US20060068739A1

公开(公告)日：2006-03-30

申请号：US11179553

申请日：2005-07-13

申请人： Koji Maeda ,  Satoshi Tanaka ,  Irei Kyu ,  Yukinori Akamine ,  Manabu Kawabe

发明人： Koji Maeda ,  Satoshi Tanaka ,  Irei Kyu ,  Yukinori Akamine ,  Manabu Kawabe

IPC分类号： H04B1/10 ,  H04B1/26

CPC分类号： H04B1/30

摘要： This invention provides a receiver in which the calibration time by repeated operations to correct phase mismatch and amplitude mismatch between I and Q signals can be reduced. The receiver comprises mixers which convert received RF signals into quadrature modulated IF signals, signal paths which filter and amplify and output the quadrature modulated signals output from the mixers, a calibration circuit which calibrates phase and amplitude mismatches between the I and Q components of the quadrature modulated signals output through the signal paths, a frequency converter which, when the mixers or the signal paths selected output calibration signals with IF frequency instead of the quadrature modulated signals, converts the calibration signals into those with a frequency higher than IF frequency, and an arithmetic operation circuit which calculates phase and amplitude mismatches from the calibration signals output by the frequency converter and outputs calculation results. The calibration circuit executes calibration, using the calculation results.

摘要翻译： 本发明提供一种接收机，其中通过重复操作来校正I和Q信号之间的相位失配和幅度失配的校准时间可以减少。 该接收机包括将接收的RF信号转换为正交调制的IF信号的混频器，对从混频器输出的正交调制信号进行滤波和放大并输出的信号路径;校准电路，其校准正交的I和Q分量之间的相位和幅度失配 调制信号通过信号路径输出，频率转换器，当混频器或信号路径选择输出具有IF频率而不是正交调制信号的校准信号时，将校准信号转换为频率高于IF频率的校准信号， 算术运算电路，从由变频器输出的校准信号计算相位和幅度失配，并输出计算结果。 校准电路使用计算结果执行校准。

公开(公告)号：US07783273B2

公开(公告)日：2010-08-24

申请号：US11543928

申请日：2006-10-06

申请人： Koji Maeda ,  Satoshi Tanaka ,  Yukinori Akamine ,  Manabu Kawabe

发明人： Koji Maeda ,  Satoshi Tanaka ,  Yukinori Akamine ,  Manabu Kawabe

IPC分类号： H04B1/10 ,  H04B7/00

CPC分类号： H04B1/30 ,  H03D3/009

摘要： The receiver, which enables rejection of image signals with higher accuracy over wider frequency band, can be provided as a low IF receiver by inputting a calibration signal of frequency fi (1≦i≦N) before reception of signals and determining the frequency response fa(z) to fd(z) of a calibrating filter in a filter mismatch calibrating circuit (FIL_CAL) 195 to make zero amplitude and phase mismatches between the I component and Q component of the quadrature demodulation signal at the frequency fIFi.

摘要翻译： 可以通过在接收信号之前输入频率fi（1＆nlE; i＆nlE; N）的校准信号，并且确定频率响应fa，可以在较宽的频带上抑制具有更高精度的图像信号的接收机作为低IF接收机 （FIL_CAL）195中的校准滤波器的（z）至fd（z），以在fIFi频率处的正交解调信号的I分量和Q分量之间产生零幅度和相位失配。