公开(公告)号：US08258037B2

公开(公告)日：2012-09-04

申请号：US12548298

申请日：2009-08-26

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

IPC分类号： H01L21/20

CPC分类号： B82Y10/00 ,  H01L21/8221 ,  H01L23/5223 ,  H01L27/0688 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.

摘要翻译： 提供了将纳米技术纳入去耦电容器设计的技术。 在一个方面，提供去耦电容器。 去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。 还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。

公开(公告)号：US08097520B2

公开(公告)日：2012-01-17

申请号：US12543544

申请日：2009-08-19

申请人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

发明人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

IPC分类号： H01L27/02

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L28/24

摘要： A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.

摘要翻译： 无源器件结构包括形成在半导体器件的无源器件区域中的未图案化的金属栅极层; 形成在未图案化的金属栅极层上的绝缘体层; 形成在所述绝缘体层上的半导体层; 以及形成在所述半导体层中的一个或多个金属接触区域; 其中所述绝缘体层防止所述金属栅极层用作流过由所述半导体层和所述一个或多个金属接触区限定的无源器件的电流的漏电流路径。

公开(公告)号：US08680651B2

公开(公告)日：2014-03-25

申请号：US13530549

申请日：2012-06-22

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： B82Y10/00 ,  H01L21/8221 ,  H01L23/5223 ,  H01L27/0688 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.

摘要翻译： 提供了将纳米技术纳入去耦电容器设计的技术。 在一个方面，提供去耦电容器。 去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。 还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。

公开(公告)号：US20120249160A1

公开(公告)日：2012-10-04

申请号：US13523120

申请日：2012-06-14

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

IPC分类号： H01L27/06 ,  G01R31/02 ,  H01H37/76 ,  H01L21/8232 ,  G01R27/08

CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

公开(公告)号：US20110127637A1

公开(公告)日：2011-06-02

申请号：US12627747

申请日：2009-11-30

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

摘要翻译： 提供了将纳米技术纳入电子保险丝（e-fuse）设计的技术。 一方面，提供了一种电熔丝结构。 电熔丝结构包括第一电极; 第一电极上的介电层，其中具有多个纳米通道; 金属硅化物纳米柱阵列，其填充介电层中的纳米通道，阵列中的每个纳米柱用作电熔丝元件; 以及与第一电极相对的金属硅化物纳米柱阵列接触的第二电极。 还提供了用于制造电熔丝结构的方法，其中还包括结合电熔丝结构的半导体器件。

公开(公告)号：US08288296B2

公开(公告)日：2012-10-16

申请号：US12763284

申请日：2010-04-20

申请人： Keith Kwong Hon Wong ,  Kangguo Cheng ,  Dechao Guo ,  Pranita Kulkarni

发明人： Keith Kwong Hon Wong ,  Kangguo Cheng ,  Dechao Guo ,  Pranita Kulkarni

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

摘要： A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric.

摘要翻译： 公开了一种替代栅极结构和制造方法。 该方法提供在同一集成电路内制造高性能FET和低泄漏FET器件。 低泄漏FET器件由具有低K电介质层和高K电介质层的混合栅极电介质制成。 高性能FET器件采用低K栅极电介质制造。

公开(公告)号：US20110254098A1

公开(公告)日：2011-10-20

申请号：US12763284

申请日：2010-04-20

申请人： Keith Kwong Hon Wong ,  Kangguo Cheng ,  Dechao Guo ,  Pranita Kulkarni

发明人： Keith Kwong Hon Wong ,  Kangguo Cheng ,  Dechao Guo ,  Pranita Kulkarni

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

摘要： A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric.

摘要翻译： 公开了一种替代栅极结构和制造方法。 该方法提供在同一集成电路内制造高性能FET和低泄漏FET器件。 低泄漏FET器件由具有低K电介质层和高K电介质层的混合栅极电介质制成。 高性能FET器件采用低K栅极电介质制造。

公开(公告)号：US08605499B2

公开(公告)日：2013-12-10

申请号：US13092247

申请日：2011-04-22

申请人： Leland Chang ,  Michael A. Guillorn ,  Dechao Guo ,  Fei Liu ,  Keith Kwong Hon Wong

发明人： Leland Chang ,  Michael A. Guillorn ,  Dechao Guo ,  Fei Liu ,  Keith Kwong Hon Wong

IPC分类号： G11C11/50

CPC分类号： H03H9/2457 ,  G11C11/404 ,  G11C23/00 ,  H03H2009/02314

摘要： Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions.

摘要翻译： 用栅电极操作纳米级悬臂梁的系统和方法。 示例性系统包括耦合到栅电极的驱动电路，其中来自电路的驱动信号可以使光束在光束的共振频率处或其附近振荡。 驱动信号包括AC分量，并且还可以包括DC分量。 替代示例系统包括纳米级悬臂梁，其中光束振荡以接触多个漏极区域。

公开(公告)号：US20110083786A1

公开(公告)日：2011-04-14

申请号：US12575968

申请日：2009-10-08

申请人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

IPC分类号： B29C65/78 ,  H01L21/683

CPC分类号： H01L21/6833 ,  B32B37/0007 ,  B32B2457/14 ,  Y10T156/1002

摘要： An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.

摘要翻译： 静电卡盘包括独立偏置的导电卡盘元件的阵列，传感器 - 导体组件的阵列，和/或传感器 - 导体组件阵列和至少一个电动卡盘的组合。 独立地或嵌入传感器 - 导体组件中的导电卡盘元件被静电地独立地偏置以补偿其上的衬底的弯曲和/或翘曲，使得衬底可以与平坦表面结合。 可以使用单个静电卡盘来减少要接合的两个基板中的一个的弯曲和翘曲，或者可以使用两个静电卡盘来最小化要接合的两个基板的弯曲和翘曲。

公开(公告)号：US08408262B2

公开(公告)日：2013-04-02

申请号：US12575968

申请日：2009-10-08

申请人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

IPC分类号： B32B41/00

CPC分类号： H01L21/6833 ,  B32B37/0007 ,  B32B2457/14 ,  Y10T156/1002

摘要： An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.

摘要翻译： 静电卡盘包括独立偏置的导电卡盘元件的阵列，传感器 - 导体组件的阵列，和/或传感器 - 导体组件阵列和至少一个电动卡盘的组合。 独立地或嵌入传感器 - 导体组件中的导电卡盘元件被静电地独立地偏置以补偿其上的衬底的弯曲和/或翘曲，使得衬底可以与平坦表面结合。 可以使用单个静电卡盘来减少要接合的两个基板中的一个的弯曲和翘曲，或者可以使用两个静电卡盘来最小化要接合的两个基板的弯曲和翘曲。