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公开(公告)号：US08344428B2
公开(公告)日：2013-01-01
申请号：US12627747
申请日：2009-11-30
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.
摘要翻译： 提供了将纳米技术纳入电子保险丝（e-fuse）设计的技术。 一方面，提供了一种电熔丝结构。 电熔丝结构包括第一电极; 第一电极上的介电层，其中具有多个纳米通道; 金属硅化物纳米柱阵列，其填充介电层中的纳米通道，阵列中的每个纳米柱用作电熔丝元件; 以及与第一电极相对的金属硅化物纳米柱阵列接触的第二电极。 还提供了用于制造电熔丝结构的方法，其中还包括结合电熔丝结构的半导体器件。
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公开(公告)号：US20120256294A1
公开(公告)日：2012-10-11
申请号：US13530549
申请日：2012-06-22
CPC分类号： B82Y10/00 , H01L21/8221 , H01L23/5223 , H01L27/0688 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.
摘要翻译： 提供了将纳米技术纳入去耦电容器设计的技术。 在一个方面，提供去耦电容器。 去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。 还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。
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公开(公告)号：US20110042786A1
公开(公告)日：2011-02-24
申请号：US12543544
申请日：2009-08-19
CPC分类号： H01L28/20 , H01L27/0629 , H01L28/24
摘要： A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.
摘要翻译： 无源器件结构包括形成在半导体器件的无源器件区域中的未图案化的金属栅极层; 形成在未图案化的金属栅极层上的绝缘体层; 形成在所述绝缘体层上的半导体层; 以及形成在所述半导体层中的一个或多个金属接触区域; 其中所述绝缘体层防止所述金属栅极层用作流过由所述半导体层和所述一个或多个金属接触区限定的无源器件的电流的漏电流路径。
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公开(公告)号：US08258037B2
公开(公告)日：2012-09-04
申请号：US12548298
申请日：2009-08-26
IPC分类号： H01L21/20
CPC分类号： B82Y10/00 , H01L21/8221 , H01L23/5223 , H01L27/0688 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.
摘要翻译： 提供了将纳米技术纳入去耦电容器设计的技术。 在一个方面，提供去耦电容器。 去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。 还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。
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公开(公告)号：US08097520B2
公开(公告)日：2012-01-17
申请号：US12543544
申请日：2009-08-19
IPC分类号： H01L27/02
CPC分类号： H01L28/20 , H01L27/0629 , H01L28/24
摘要： A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.
摘要翻译： 无源器件结构包括形成在半导体器件的无源器件区域中的未图案化的金属栅极层; 形成在未图案化的金属栅极层上的绝缘体层; 形成在所述绝缘体层上的半导体层; 以及形成在所述半导体层中的一个或多个金属接触区域; 其中所述绝缘体层防止所述金属栅极层用作流过由所述半导体层和所述一个或多个金属接触区限定的无源器件的电流的漏电流路径。
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公开(公告)号：US08680651B2
公开(公告)日：2014-03-25
申请号：US13530549
申请日：2012-06-22
CPC分类号： B82Y10/00 , H01L21/8221 , H01L23/5223 , H01L27/0688 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.
摘要翻译： 提供了将纳米技术纳入去耦电容器设计的技术。 在一个方面，提供去耦电容器。 去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。 还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。
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公开(公告)号：US20110127637A1
公开(公告)日：2011-06-02
申请号：US12627747
申请日：2009-11-30
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.
摘要翻译： 提供了将纳米技术纳入电子保险丝（e-fuse）设计的技术。 一方面，提供了一种电熔丝结构。 电熔丝结构包括第一电极; 第一电极上的介电层，其中具有多个纳米通道; 金属硅化物纳米柱阵列，其填充介电层中的纳米通道，阵列中的每个纳米柱用作电熔丝元件; 以及与第一电极相对的金属硅化物纳米柱阵列接触的第二电极。 还提供了用于制造电熔丝结构的方法，其中还包括结合电熔丝结构的半导体器件。
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公开(公告)号：US09059006B2
公开(公告)日：2015-06-16
申请号：US13523120
申请日：2012-06-14
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L23/52 , H01L29/10 , H01L27/06 , H01L23/525 , H01L27/112 , H01L29/66 , H01L29/49 , H01L29/78
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触点中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。
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公开(公告)号：US08237457B2
公开(公告)日：2012-08-07
申请号：US12503116
申请日：2009-07-15
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。
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公开(公告)号：US20110012629A1
公开(公告)日：2011-01-20
申请号：US12503116
申请日：2009-07-15
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Rajeevakumar V. Thekkemadathil , Keith Kwong Hon Wong
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。
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