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    REPLACEMENT-GATE-COMPATIBLE PROGRAMMABLE ELECTRICAL ANTIFUSE
    1.
    发明申请
    REPLACEMENT-GATE-COMPATIBLE PROGRAMMABLE ELECTRICAL ANTIFUSE 有权
    替代可控可编程电抗器

    公开(公告)号：US20110012629A1

    公开(公告)日：2011-01-20

    申请号：US12503116

    申请日：2009-07-15

    申请人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

    发明人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

    IPC分类号： G01R27/08 ,  H01L27/06 ,  H01L21/28 ,  H01H37/76

    CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

    摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

    Replacement-gate-compatible programmable electrical antifuse
    4.
    发明授权
    Replacement-gate-compatible programmable electrical antifuse 有权
    替换门兼容可编程电气反熔丝

    公开(公告)号：US08237457B2

    公开(公告)日：2012-08-07

    申请号：US12503116

    申请日：2009-07-15

    申请人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

    发明人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Thekkemadathil V. Rajeevakumar ,  Keith Kwong Hon Wong

    IPC分类号： G01R27/08 ,  H01L23/52 ,  H01L29/10

    CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

    摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

    Nanopillar E-fuse structure and process
    5.
    发明授权
    Nanopillar E-fuse structure and process 有权
    纳米棒电子熔丝结构及工艺

    公开(公告)号：US08344428B2

    公开(公告)日：2013-01-01

    申请号：US12627747

    申请日：2009-11-30

    申请人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

    发明人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

    摘要翻译： 提供了将纳米技术纳入电子保险丝（e-fuse）设计的技术。 一方面，提供了一种电熔丝结构。 电熔丝结构包括第一电极; 第一电极上的介电层，其中具有多个纳米通道; 金属硅化物纳米柱阵列，其填充介电层中的纳米通道，阵列中的每个纳米柱用作电熔丝元件; 以及与第一电极相对的金属硅化物纳米柱阵列接触的第二电极。 还提供了用于制造电熔丝结构的方法，其中还包括结合电熔丝结构的半导体器件。

    Nanopillar Decoupling Capacitor
    6.
    发明申请
    Nanopillar Decoupling Capacitor 有权
    纳米棒去耦电容器

    公开(公告)号：US20120256294A1

    公开(公告)日：2012-10-11

    申请号：US13530549

    申请日：2012-06-22

    申请人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

    发明人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

    IPC分类号： H01L29/02 ,  H01L21/02

    CPC分类号： B82Y10/00 ,  H01L21/8221 ,  H01L23/5223 ,  H01L27/0688 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.

    摘要翻译： 提供了将纳米技术纳入去耦电容器设计的技术。 在一个方面，提供去耦电容器。 去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。 还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。

    INTEGRATION OF PASSIVE DEVICE STRUCTURES WITH METAL GATE LAYERS
    7.
    发明申请
    INTEGRATION OF PASSIVE DEVICE STRUCTURES WITH METAL GATE LAYERS 有权
    被动设备结构与金属盖层的集成

    公开(公告)号：US20110042786A1

    公开(公告)日：2011-02-24

    申请号：US12543544

    申请日：2009-08-19

    申请人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

    发明人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

    IPC分类号： H01L29/86 ,  H01L21/02

    CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L28/24

    摘要： A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.

    摘要翻译： 无源器件结构包括形成在半导体器件的无源器件区域中的未图案化的金属栅极层; 形成在未图案化的金属栅极层上的绝缘体层; 形成在所述绝缘体层上的半导体层; 以及形成在所述半导体层中的一个或多个金属接触区域; 其中所述绝缘体层防止所述金属栅极层用作流过由所述半导体层和所述一个或多个金属接触区限定的无源器件的电流的漏电流路径。

    Nanopillar decoupling capacitor
    8.
    发明授权
    Nanopillar decoupling capacitor 有权
    纳米管去耦电容器

    公开(公告)号：US08258037B2

    公开(公告)日：2012-09-04

    申请号：US12548298

    申请日：2009-08-26

    申请人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

    发明人： Satya N. Chakravarti ,  Dechao Guo ,  Huiming Bu ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/20

    CPC分类号： B82Y10/00 ,  H01L21/8221 ,  H01L23/5223 ,  H01L27/0688 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.

    摘要翻译： 提供了将纳米技术纳入去耦电容器设计的技术。 在一个方面，提供去耦电容器。 去耦电容器包括第一电极; 与第一电极相邻的中间层，其中具有多个纳米通道; 在中间层上形成并衬在纳米通道上的保形介电层; 以及第二电极，其至少一部分由填充中间层中的纳米通道的纳米柱阵列形成。 还提供了用于制造去耦电容器的方法，以及包含去耦电容器设计的半导体器件。

    Integration of passive device structures with metal gate layers
    9.
    发明授权
    Integration of passive device structures with metal gate layers 有权
    无源器件结构与金属栅极层的集成

    公开(公告)号：US08097520B2

    公开(公告)日：2012-01-17

    申请号：US12543544

    申请日：2009-08-19

    申请人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

    发明人： Huiming Bu ,  Satya N. Chakravarti ,  Dechao Guo ,  Keith Kwong Hon Wong

    IPC分类号： H01L27/02

    CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L28/24

    摘要： A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.

    摘要翻译： 无源器件结构包括形成在半导体器件的无源器件区域中的未图案化的金属栅极层; 形成在未图案化的金属栅极层上的绝缘体层; 形成在所述绝缘体层上的半导体层; 以及形成在所述半导体层中的一个或多个金属接触区域; 其中所述绝缘体层防止所述金属栅极层用作流过由所述半导体层和所述一个或多个金属接触区限定的无源器件的电流的漏电流路径。

    Method and structure for improving uniformity of passive devices in metal gate technology
    10.
    发明授权
    Method and structure for improving uniformity of passive devices in metal gate technology 有权
    用于提高金属栅极技术中无源器件均匀性的方法和结构

    公开(公告)号：US08053317B2

    公开(公告)日：2011-11-08

    申请号：US12541933

    申请日：2009-08-15

    申请人： Satya N. Chakravarti ,  Dechao Guo ,  Wilfried Ernst-August Haensch ,  Pranita Kulkarni ,  Fei Liu ,  Philip J. Oldiges ,  Keith Kwong Hon Wong

    发明人： Satya N. Chakravarti ,  Dechao Guo ,  Wilfried Ernst-August Haensch ,  Pranita Kulkarni ,  Fei Liu ,  Philip J. Oldiges ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/0629 ,  H01L21/82345

    摘要： Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.

    摘要翻译： 形成半导体器件的方法包括以下步骤：获得具有逻辑区域和STI区域的半导体衬底; 依次沉积高K材料，金属栅极，第一硅和硬掩模层; 从逻辑区域去除硬掩模和第一硅层; 在半导体衬底上施加第二层硅，使得逻辑区域具有高K材料，金属栅极和第二硅层，并且STI区域具有高K材料，金属栅极，第一硅，硬掩模和第二硅层。 也可以在STI区域中的金属栅极层和第一硅层之间存在第二硬掩模层。 在STI区域中的金属栅极层和第一硅层之间也可以存在硬掩模层，但在STI区域中的第一和第二硅层之间没有硬掩模层。