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    Dynamic early indication system for a computer
    11.
    发明授权
    Dynamic early indication system for a computer 失效
    电脑动态早期指示系统

    公开(公告)号：US06631434B1

    公开(公告)日：2003-10-07

    申请号：US09440396

    申请日：1999-11-15

    申请人： Scott C. Johnson ,  Rodney S. Canion

    发明人： Scott C. Johnson ,  Rodney S. Canion

    IPC分类号： G06F948

    CPC分类号： G06F13/24

    摘要： A dynamic early indication system for a computer includes a processor subsystem logic that performs a subsystem function, an early indicator, indication logic, and a driver that is executed by the processor in response to an indication to perform processing. The indication logic may be coupled to the subsystem logic and early indicator to provide an indication that informs the processor when processing associated with the subsystem function is needed at a completion time of the subsystem function. The indication may be provided before the completion time of the subsystem function if the early indicator represents early indication. The driver controls the early indicator to improve efficiency of subsystem processing.

    摘要翻译： 用于计算机的动态早期指示系统包括执行子系统功能的处理器子系统逻辑，早期指示符，指示逻辑和由处理器响应于执行处理的指示而执行的驱动器。 指示逻辑可以耦合到子系统逻辑和早期指示符，以提供通知处理器在子系统功能的完成时间需要与子系统功能相关联的处理的指示。 如果早期指示符表示早期指示，则可以在子系统功能的完成时间之前提供指示。 驾驶员控制早期指标以提高子系统处理的效率。

    Network abstraction and isolation layer for masquerading machine identity of a computer
    14.
    发明授权
    Network abstraction and isolation layer for masquerading machine identity of a computer 有权
    网络抽象和隔离层，用于伪装计算机的机器身份

    公开(公告)号：US08331391B2

    公开(公告)日：2012-12-11

    申请号：US12838009

    申请日：2010-07-16

    申请人： Scott C. Johnson ,  Dave D. McCrory

    发明人： Scott C. Johnson ,  Dave D. McCrory

    IPC分类号： H04L12/56 ,  H04J1/16

    CPC分类号： H04L63/0407 ,  H04L63/16

    摘要： A network abstraction and isolation layer (NAIL) for masquerading the machine identity of a computer in a network to enable the computer to communicate in the network with a different machine identity including an isolated network interface for communicating with the computer, an abstraction network interface for communicating with a network device coupled to the network, and control instructions or device. The control instructions or device performs machine identity translation to masquerade machine identity of the computer relative to the network. Machine identity masquerading includes selectively translating any one or more of an IP address, a MAC address, a machine name, a system identifier, and a DNS Name in the header or payload of communication packets.

    摘要翻译： 一种用于伪装网络中的计算机的机器标识的网络抽象和隔离层（NAIL），以使计算机能够在网络中与不同的机器标识进行通信，包括用于与计算机进行通信的隔离网络接口，用于 与耦合到网络的网络设备进行通信，以及控制指令或设备。 控制指令或设备执行机器标识转换，以相对于网络伪装计算机的机器标识。 机器识别伪装包括在通信包的头部或有效载荷中选择性地翻译IP地址，MAC地址，机器名称，系统标识符和DNS名称中的一个或多个。

    Controller for clock skew determination and reduction based on a lead count over multiple clock cycles
    15.
    发明授权
    Controller for clock skew determination and reduction based on a lead count over multiple clock cycles 有权
    控制器用于在多个时钟周期内基于引脚数的时钟偏差确定和减少

    公开(公告)号：US07770049B1

    公开(公告)日：2010-08-03

    申请号：US11385328

    申请日：2006-03-21

    申请人： Shawn Searles ,  Scott C. Johnson ,  Donald Walters ,  Ravinder Rachala

    发明人： Shawn Searles ,  Scott C. Johnson ,  Donald Walters ,  Ravinder Rachala

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10

    摘要： Clock skew may be detected measured and compensated for using phase detectors and variable delay adjusters. Phase detectors may be distributed throughout a clock distribution network and may be configured to analyze two clock signals to determine how often one signal leads the other. The output of the phase detectors may be measured and counted over a large number of clock cycles. The difference between the number of times one signal leads or lags behind the other may be used to determine the amount of delay to apply to the leading clock signal in order to minimize (reduce) skew between the two clock signals. The same techniques for detecting and measuring clock skew may also be used to detect and measure jitter in the clock signals. By configuring variable delay adjusters on clock signals, the amount of jitter in the clock signals can be measured or characterized.

    摘要翻译： 可以使用相位检测器和可变延迟调节器测量和补偿时钟偏移。 相位检测器可以分布在整个时钟分配网络中，并且可以被配置为分析两个时钟信号以确定一个信号引导另一个信号的频率。 可以在大量时钟周期上测量和计数相位检测器的输出。 可以使用一个信号引导或滞后于另一个信号的次数之间的差异来确定应用于前导时钟信号的延迟量，以便最小化（减少）两个时钟信号之间的偏差。 用于检测和测量时钟偏移的相同技术也可用于检测和测量时钟信号中的抖动。 通过在时钟信号上配置可变延迟调节器，可以测量或表征时钟信号中的抖动量。

    Network abstraction and isolation layer for masquerading machine identity of a computer
    16.
    发明授权
    Network abstraction and isolation layer for masquerading machine identity of a computer 有权
    网络抽象和隔离层，用于伪装计算机的机器身份

    公开(公告)号：US07769004B2

    公开(公告)日：2010-08-03

    申请号：US10950355

    申请日：2004-09-24

    申请人： Scott C. Johnson ,  Dave D. McCrory

    发明人： Scott C. Johnson ,  Dave D. McCrory

    IPC分类号： H04L12/28

    CPC分类号： H04L63/0407 ,  H04L63/16

    摘要： A network abstraction and isolation layer (NAIL) for masquerading the machine identity of a computer in a network to enable the computer to communicate in the network with a different machine identity including an isolated network interface for communicating with the computer, an abstraction network interface for communicating with a network device coupled to the network, and control logic. The control logic is coupled to the isolated and abstraction network interfaces and performs machine identity translation to masquerade machine identity of the computer relative to the network. Machine identity masquerading includes selectively translating any one or more of an IP address, a MAC address, a machine name, a system identifier, and a DNS Name in the header or payload of communication packets.

    摘要翻译： 一种用于伪装网络中的计算机的机器标识的网络抽象和隔离层（NAIL），以使计算机能够在网络中与不同的机器标识进行通信，包括用于与计算机进行通信的隔离网络接口，用于 与耦合到网络的网络设备进行通信，以及控制逻辑。 控制逻辑耦合到隔离和抽象网络接口，并执行机器标识转换，以相对于网络伪装计算机的机器标识。 机器识别伪装包括在通信包的头部或有效载荷中选择性地翻译IP地址，MAC地址，机器名称，系统标识符和DNS名称中的一个或多个。

    System and technique for power management of a universal asynchronous receiver/transmitter by automatic clock gating
    20.
    发明授权
    System and technique for power management of a universal asynchronous receiver/transmitter by automatic clock gating 失效
    通过自动时钟门控对通用异步接收机/发射机进行电源管理的系统和技术

    公开(公告)号：US5661751A

    公开(公告)日：1997-08-26

    申请号：US602261

    申请日：1996-02-15

    申请人： Scott C. Johnson

    发明人： Scott C. Johnson

    IPC分类号： H04L25/38 ,  G06F1/32 ,  G06F13/38 ,  H04L7/04 ,  H04L25/40 ,  H04B1/38

    CPC分类号： G06F1/3215 ,  G06F13/385 ,  Y02B60/1235

    摘要： A clock control unit is provided that controls the gating of a clock signal received by an internal baud generator of a universal asynchronous receiver/transmitter (UART) circuit during an active mode. The clock control unit monitors the UART circuit to determine whether the UART is currently idle. If the clock control unit determines that the UART is idle, the clock signal is gated by a synchronous clock gate circuit. Accordingly, the clock signal is not provided to the baud generator, and a corresponding baud rate signal that normally clocks the receiver state machine of the UART is not generated. Power consumption of the UART is thereby significantly reduced. When a certain predetermined system activity is thereafter detected by the clock control unit that indicates a need for activation of the UART, the clock control unit asserts a clock enable signal that causes the synchronous clock gate circuit to pass the clock signal to an input of the baud generator. In one embodiment, the clock control unit causes the clock signal to be degated if the receipt of serial data is detected at the serial input line of the UART, if the receiver state machine is currently active, if the receiver FIFO and buffer register is not empty, if the transmitter FIFO and holding register is not empty, or if the transmitter state machine is active.

    摘要翻译： 提供时钟控制单元，用于在活动模式期间控制由通用异步收发器（UART）电路的内部波特发生器接收的时钟信号的门控。 时钟控制单元监视UART电路，以确定UART当前是否处于空闲状态。 如果时钟控制单元确定UART处于空闲状态，则时钟信号由同步时钟门电路门控。 因此，时钟信号不提供给波特率发生器，并且不产生通常对UART的接收状态机进行时钟的对应的波特率信号。 因此UART的功耗显着降低。 当由时钟控制单元此后检测到指示需要激活UART的某一预定系统活动时，时钟控制单元断言时钟使能信号，该时钟使能信号使同步时钟门电路将时钟信号传递到 波特发生器 在一个实施例中，如果在UART的串行输入线上检测到串行数据的接收，则时钟控制单元导致时钟信号被消除，如果接收器状态机当前有效，则如果接收器FIFO和缓冲寄存器不是 如果发送器FIFO和保持寄存器不为空，或发送状态机是否处于活动状态，则为空。