摘要:
In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.
摘要:
Exemplary embodiments of the invention provide a reference harmonic oscillator integrated circuit having three or more terminals, with systems and methods for calibrating the harmonic oscillator to a selected first frequency using a limited number of terminals. An exemplary apparatus comprises: a reference harmonic oscillator, a first terminal to receive a supply voltage, a second terminal to receive a ground potential, a third terminal to provide an output signal having an output frequency, and may also include a fourth terminal. One of the first, second, third or fourth terminals is further adapted for input of a calibration of the first frequency. The exemplary apparatus may enter calibration and testing modes in response to various commands such as a calibration mode signal, and may also be configured through one of the terminals for output frequency selection, spread-spectrum output, and output voltage levels.
摘要:
In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.
摘要:
In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.
摘要:
In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.
摘要:
Exemplary embodiments of the invention provide a reference harmonic oscillator integrated circuit having three or more terminals, with systems and methods for calibrating the harmonic oscillator to a selected first frequency using a limited number of terminals. An exemplary apparatus comprises: a reference harmonic oscillator, a first terminal to receive a supply voltage, a second terminal to receive a ground potential, a third terminal to provide an output signal having an output frequency, and may also include a fourth terminal. One of the first, second, third or fourth terminals is further adapted for input of a calibration of the first frequency. The exemplary apparatus may enter calibration and testing modes in response to various commands such as a calibration mode signal, and may also be configured through one of the terminals for output frequency selection, spread-spectrum output, and output voltage levels.
摘要:
In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.
摘要:
A reference signal generator includes an integrated circuit substrate having a semiconductor resonator therein. The resonator includes an inductor extending adjacent a first surface of the integrated circuit substrate. A vertically-stacked composite of at least first and second electrically insulating dielectric layers is provided on the integrated circuit substrate. The vertically-stacked composite covers a portion of the first surface, which extends opposite the inductor. A first electrically conductive shielding layer is provided on a portion of the second electrically insulating dielectric layer extending opposite the inductor. The first electrically conductive shielding layer may encapsulate exposed portions of the first and second electrically insulating dielectric layers. The shielding layer may operate as an electromagnetic shield between the inductor and an external structure, such as an integrated circuit package, and also shield against environmental contamination (e.g., external moisture penetration).
摘要:
A divider for use in an integrated circuit chip, such as a clock generator chip, includes a ramp generator circuit configured to generate a ramp signal and a synchronous detector circuit configured to receive the ramp signal and an input clock signal and to responsively control the ramp signal generator circuit to generate an output clock signal at an output of the synchronous detector circuit. In some embodiments, the synchronous detector circuit may include a voltage threshold detector circuit configured to receive the ramp signal and to generate a detection signal responsive thereto and a synchronous latch circuit having a clock input configured to receive the input clock signal and a data input configured to receive the detection signal. The synchronous latch circuit may be configured to control the ramp generator circuit.
摘要:
An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.