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11.发明授权公开(公告)号：US11797396B2
公开(公告)日：2023-10-24
申请号：US16944039
申请日：2020-07-30
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Jason Bellorado , Ara Patapoutian , Marcus Marrow
CPC classification number: G06F11/1471 , G06F3/064 , G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F11/0772
Abstract: An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.
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公开(公告)号：US11658669B2
公开(公告)日：2023-05-23
申请号：US17582376
申请日：2022-01-24
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: H03M1/06 , G11B5/012 , G11B5/027 , G11B20/10324 , H03G3/30 , H03G2201/103
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.
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公开(公告)号：US20220399037A1
公开(公告)日：2022-12-15
申请号：US17890580
申请日：2022-08-18
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.
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公开(公告)号：US10936003B1
公开(公告)日：2021-03-02
申请号：US15803672
申请日：2017-11-03
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Trung Thuc Nguyen , Wing Fai Hui , Kin Ming Chan
Abstract: Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.
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公开(公告)号：US10803902B1
公开(公告)日：2020-10-13
申请号：US16104929
申请日：2018-08-19
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Marcus Marrow , Jason Bellorado
Abstract: Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.
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Patent Agency Ranking
公开(公告)号：US10694007B1
公开(公告)日：2020-06-23
申请号：US16372225
申请日：2019-04-01
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow
Abstract: Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.
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公开(公告)号：US10608808B1
公开(公告)日：2020-03-31
申请号：US16134293
申请日：2018-09-18
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow , Zheng Wu
Abstract: In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.
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公开(公告)号：US10607648B1
公开(公告)日：2020-03-31
申请号：US16025363
申请日：2018-07-02
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Marcus Marrow , Jason Bellorado
Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader so that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.
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公开(公告)号：US10483999B1
公开(公告)日：2019-11-19
申请号：US15997571
申请日：2018-06-04
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Vincent Bellorado , Marcus Marrow
Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.
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公开(公告)号：US10382166B1
公开(公告)日：2019-08-13
申请号：US15439450
申请日：2017-02-22
Applicant: Seagate Technology LLC
Inventor： Vincent Brendan Ashe , Jason Vincent Bellorado , Marcus Marrow
Abstract: Systems and methods are disclosed for constrained receiver parameter optimization. Two parameter optimization functions may be applied, with one function providing constraints on the results of the second function in order to determine a parameter set to apply in the receiver. A method may comprise determining a first parameter set based on a first function, determining a second parameter set based on a second function different from the first function, and determining a third parameter set by using the first parameter set to define a subset of a parameter space to which to limit values from the second parameter set. In certain embodiments, a least squares function may be used to constrain the results of a general cost function.
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