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公开(公告)号:US12230172B2
公开(公告)日:2025-02-18
申请号:US18263159
申请日:2022-01-18
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shunpei Yamazaki , Yosuke Tsukamoto , Koji Kusunoki , Hisao Ikeda , Akio Endo , Yoshiaki Oikawa , Hideki Uochi
IPC: G09G3/00 , G02B27/01 , G06F3/01 , G09G3/3233
Abstract: A semiconductor device having favorable display quality is provided. The semiconductor device is provided with a display portion, a line-of-sight sensor portion, a control portion, and an arithmetic portion. The line-of-sight sensor portion has a function of obtaining first information showing a direction of a user's line of sight. The arithmetic portion has a function of determining a first region including a gaze point of the user on the display portion with use of the first information and a function of increasing a definition of an image displayed on the first region. Light emitted from the display portion may be used to obtain the first information showing the direction of the line of sight.
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公开(公告)号:US12229661B2
公开(公告)日:2025-02-18
申请号:US18510784
申请日:2023-11-16
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takahiko Ishizu , Takayuki Ikeda , Atsuo Isobe , Atsushi Miyaguchi , Shunpei Yamazaki
IPC: G06N3/065 , G06F1/3234 , G06F7/544 , G06T1/20
Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.
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公开(公告)号:US12224293B2
公开(公告)日:2025-02-11
申请号:US18399990
申请日:2023-12-29
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shunpei Yamazaki , Yuichi Sato , Hitoshi Nakayama
Abstract: A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.
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公开(公告)号:US12218251B2
公开(公告)日:2025-02-04
申请号:US18626594
申请日:2024-04-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Tatsuya Honda , Masashi Tsubuku , Yusuke Nonaka , Takashi Shimazu , Shunpei Yamazaki
IPC: H01L29/786 , G02F1/1333 , G02F1/1337 , G02F1/1339 , G02F1/1343 , H01L27/12 , H01L29/04 , H01L29/24 , H01L29/51 , H01L29/66 , H01L21/02 , H10K59/121
Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
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公开(公告)号:US12205979B2
公开(公告)日:2025-01-21
申请号:US18236029
申请日:2023-08-21
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shunpei Yamazaki , Takayuki Ikeda
Abstract: A novel functional panel that is highly convenient or highly reliable is provided. The functional panel includes a first pixel. The first pixel includes a first element, a color conversion layer, and a first functional layer. The first functional layer is positioned between the first element and the color conversion layer. The first element has a function of emitting light and contains gallium nitride. The color conversion layer has a function of converting the color of light emitted from the first element into a different color. The first functional layer includes a first insulating film and a pixel circuit. The first insulating film includes a region positioned between the pixel circuit and the first element, and has an opening. The pixel circuit includes a first transistor. The first transistor includes a first oxide semiconductor film and is electrically connected to the first element through the opening.
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公开(公告)号:US12205892B2
公开(公告)日:2025-01-21
申请号:US17297863
申请日:2019-11-20
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Akio Suzuki , Atsushi Miyaguchi , Shunpei Yamazaki
IPC: H01L23/528 , H01L23/31 , H01L23/367 , H01L29/786
Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a silicon substrate and a device provided above the silicon substrate. The device includes a transistor and a conductor. The transistor includes a metal oxide in a channel formation region. Conductivity is imparted to the silicon substrate. The conductor is electrically connected to each of a drain of the transistor and the silicon substrate through an opening provided in the device. Heat of the drain of the transistor can be efficiently released through the silicon substrate.
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公开(公告)号:US12199187B2
公开(公告)日:2025-01-14
申请号:US18422049
申请日:2024-01-25
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shunpei Yamazaki , Masayuki Sakakura
IPC: H01L29/10 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/04 , H01L29/417 , H01L29/423 , H01L29/786 , H01L21/8238
Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
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公开(公告)号:US12183743B2
公开(公告)日:2024-12-31
申请号:US18231902
申请日:2023-08-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei Yamazaki , Hiroki Ohara , Toshinari Sasaki , Kosei Noda , Hideaki Kuwabara
IPC: H01L27/12 , G02F1/1333 , G02F1/1337 , G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L29/24 , H01L29/51 , H01L29/786
Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
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公开(公告)号:US12176439B2
公开(公告)日:2024-12-24
申请号:US17428753
申请日:2020-02-13
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Shunpei Yamazaki , Erika Takahashi , Tsutomu Murakawa , Shinya Sasagawa , Katsuaki Tochibayashi
IPC: H01L29/786 , H01L29/04 , H01L29/66
Abstract: A semiconductor device with small fluctuations in transistor characteristics can be provided. The semiconductor device includes a first oxide, a second oxide and a third oxide over the first oxide, a first conductor over the second oxide, a second conductor over the third oxide, a fourth oxide over the first oxide and between the second oxide and the third oxide, a first insulator over the fourth oxide, and a third conductor over the first insulator. The first oxide includes a groove in a region not overlapping with the second oxide and the third oxide. The first oxide includes a first layered crystal substantially parallel to the surface where the first oxide is formed. In the groove, the fourth oxide includes a second layered crystal substantially parallel to the surface where the first oxide is formed. A concentration of aluminum atoms at an interface between the first oxide and the fourth oxide and in the vicinity of the interface is less than or equal to 5.0 atomic %.
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20.
公开(公告)号:US12165557B2
公开(公告)日:2024-12-10
申请号:US18201823
申请日:2023-05-25
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Susumu Kawashima , Koji Kusunoki , Kei Takahashi , Shunpei Yamazaki
IPC: G09G3/20 , G09G3/3233 , H01L27/12 , H01L29/786 , H04N23/50 , H04N23/57 , H10B99/00
Abstract: To provide a display device capable of displaying a plurality of images by superimposition using a plurality of memory circuits provided in a pixel. A plurality of memory circuits are provided in a pixel, and signals corresponding to images for superimposition are retained in each of the plurality of memory circuits. In the pixel, the signals corresponding to the images for superimposition are added to each of the plurality of memory circuits. The signals are added to the signals retained in the memory circuits by capacitive coupling. A display element can display an image corresponding to a signal in which a signal written to a pixel through a wiring is added to the signals retained in the plurality of memory circuits. Reduction in the amount of arithmetic processing for displaying images by superimposition can be achieved.
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