公开(公告)号：US09640642B2

公开(公告)日：2017-05-02

申请号：US15190677

申请日：2016-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

公开(公告)号：US11894397B2

公开(公告)日：2024-02-06

申请号：US17729017

申请日：2022-04-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Yuichi Sato ,  Hitoshi Nakayama

IPC: H01L27/12 ,  H01L29/24 ,  H10B12/00

CPC classification number: H01L27/1255 ,  H01L27/1225 ,  H01L29/24 ,  H10B12/30

Abstract: A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.

公开(公告)号：US09379136B2

公开(公告)日：2016-06-28

申请号：US14334012

申请日：2014-07-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

Abstract translation: 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

公开(公告)号：US09837513B2

公开(公告)日：2017-12-05

申请号：US15498782

申请日：2017-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Hitoshi Nakayama ,  Masashi Tsubuku ,  Daigo Shimada

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/66

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

公开(公告)号：US11355530B2

公开(公告)日：2022-06-07

申请号：US17041852

申请日：2019-04-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Yuichi Sato ,  Hitoshi Nakayama

IPC: H01L27/12 ,  H01L29/24 ,  H01L27/108

Abstract: A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.

公开(公告)号：US12224293B2

公开(公告)日：2025-02-11

申请号：US18399990

申请日：2023-12-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Yuichi Sato ,  Hitoshi Nakayama

IPC: H01L27/13 ,  H01L27/12 ,  H01L29/24 ,  H10B12/00

Abstract: A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.

公开(公告)号：US11257960B2

公开(公告)日：2022-02-22

申请号：US16981148

申请日：2019-03-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Yuichi Sato ,  Hitoshi Nakayama

IPC: H01L29/786 ,  H01L29/22 ,  H01L29/51

Abstract: A semiconductor device having high on-state current and favorable reliability is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a first conductor over the third oxide; a second conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a third conductor positioned over the second insulator and overlapping with the second oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide, and the conductivity of the fourth oxide is higher than the conductivity of the second oxide.

公开(公告)号：US09373708B2

公开(公告)日：2016-06-21

申请号：US14718763

申请日：2015-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Hitoshi Nakayama ,  Hiroshi Fujiki

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/36 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

Abstract translation: 为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。 通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。 在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层， 除了含有氯的气体之外，还使用含有氧或氟的气体。