公开(公告)号：US20220375521A1

公开(公告)日：2022-11-24

申请号：US17773887

申请日：2020-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Hitoshi KUNITAKE

IPC: G11C14/00 ,  H01L27/11582

Abstract: A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.

公开(公告)号：US20220366845A1

公开(公告)日：2022-11-17

申请号：US17723613

申请日：2022-04-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime KIMURA ,  Takayuki IKEDA

IPC: G09G3/3225

Abstract: A semiconductor device includes first to tenth transistors and first to fourth capacitors. Gates of the first and the fourth transistors are electrically connected to each other. First terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor. A second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. Gates of the second, seventh, and tenth transistors are electrically connected to first terminals of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor.

公开(公告)号：US20220359592A1

公开(公告)日：2022-11-10

申请号：US17633242

申请日：2020-08-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi YONEDA ,  Yusuke NEGORO ,  Takayuki IKEDA ,  Shunpei YAMAZAKI

IPC: H01L27/146

Abstract: An imaging device that has an image processing function and is capable of a high-speed operation is provided. The imaging device, which has an additional function such as image processing, can retain analog data obtained by an image capturing operation in a pixel and extract data obtained by multiplying the analog data by a predetermined weight coefficient. In the imaging device, some of potentials used for an arithmetic operation in pixels are generated by redistribution of charge with which wirings are charged. This enables an arithmetic operation to be performed at high speed with low power consumption, compared with the case where the potentials are supplied from another circuit to the pixels.

公开(公告)号：US20220345095A1

公开(公告)日：2022-10-27

申请号：US17619669

申请日：2020-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Takayuki IKEDA ,  Kiyoshi KATO ,  Yuichi YANAGISAWA ,  Shota MIZUKAMI ,  Kazuki TSUDA

IPC: H03F3/195 ,  H03F1/02 ,  H01L29/786

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

公开(公告)号：US20220286090A1

公开(公告)日：2022-09-08

申请号：US17607943

申请日：2020-04-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyotaka KIMURA ,  Takeya HIROSE ,  Hidetomo KOBAYASHI ,  Takayuki IKEDA

IPC: H03D7/12 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a mixer circuit including a digital-analog converter circuit, a control circuit for controlling the digital-analog converter circuit, a power source control switch, and a plurality of Gilbert circuits. The plurality of Gilbert circuits each include an analog potential holding circuit for holding an analog potential output from the digital-analog converter circuit. The control circuit has a function of outputting a signal for controlling the analog potential holding circuit and the digital-analog converter circuit. The power source control switch has a function of stopping supply of a power source voltage to the control circuit in a period during which the analog potential held in the analog potential holding circuit is not updated. The analog potential holding circuit includes a first transistor. The first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region.

公开(公告)号：US20220255579A1

公开(公告)日：2022-08-11

申请号：US17616539

申请日：2020-06-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Hitoshi KUNITAKE

IPC: H04B1/44 ,  H03K17/16 ,  H03K17/693

Abstract: A communication device capable of transmitting and receiving high-potential signals is provided. The communication device includes a duplexer including first to fourth transistors, a transmission terminal, a reception terminal, an antenna terminal, and first and second control terminals. The transmission terminal is electrically connected to one of a source and a drain of each of the first and second transistors. The reception terminal is electrically connected to one of a source and a drain of each of the third and fourth transistors. The antenna terminal is electrically connected to the other of the source and the drain of each of the second and fourth transistors. The first control terminal is electrically connected to gates of the second and third transistors. The second control terminal is electrically connected to gates of the first and fourth transistors. A semiconductor of each of the first to fourth transistors contains a metal oxide.

公开(公告)号：US20220255511A1

公开(公告)日：2022-08-11

申请号：US17611921

申请日：2020-05-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hajime KIMURA ,  Takayuki IKEDA

IPC: H03F3/19

Abstract: A communication device that can transmit and receive a signal with a large amplitude is provided. The communication device includes an amplifier circuit including first to fourth transistors, first to fourth bias transistors, first to fourth loads, and first to fourth terminals. The drains of the first to fourth transistors are electrically connected to the sources of the first to fourth bias transistors. The sources of the first to fourth transistors are electrically connected to power supply lines. The gates of the first and second bias transistors are electrically connected to a first wiring, and the gates of the third and fourth bias transistors are electrically connected to a second wiring. The first to fourth terminals are electrically connected to the gates of the first to fourth transistors, the drains of the third, fourth, first, and second bias transistors, and the first to fourth loads.

公开(公告)号：US20220190398A1

公开(公告)日：2022-06-16

申请号：US17439436

申请日：2020-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Takeshi AOKI ,  Munehiro KOZUMA ,  Kei TAKAHASHI ,  Shunpei YAMAZAKI

IPC: H01M10/42

Abstract: A semiconductor device with reduced power consumption is provided. With three transistors, potentials of two nodes are switched and a voltage is detected. One of a source and a drain of a first transistor is electrically connected to a first terminal. The other of the source and the drain of the first transistor is electrically connected to a non-inverting input of a comparator through a first node. One of a source and a drain of a second transistor is electrically connected to a second terminal. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor through a second node. The other of the source and the drain of the third transistor is electrically connected to a third terminal. A first capacitor is provided between the first node and the second node. An inverting input of the comparator is electrically connected to a fourth terminal. An output of the comparator is electrically connected to a fifth terminal.

公开(公告)号：US20220164641A1

公开(公告)日：2022-05-26

申请号：US17588613

申请日：2022-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Takayuki IKEDA ,  Atsuo ISOBE ,  Atsushi MIYAGUCHI ,  Shunpei YAMAZAKI

IPC: G06N3/063 ,  G06F7/544 ,  G06T1/20 ,  G06F1/3234

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.

公开(公告)号：US20220103772A1

公开(公告)日：2022-03-31

申请号：US17422580

申请日：2020-01-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA

IPC: H04N5/378 ,  H04N5/369 ,  H01L27/146

Abstract: An imaging device having a memory function is provided. Alternatively, an imaging device suitable for taking images of a moving object is provided. The imaging device includes a first to third layers; the second layer is provided between the first and the third layer; the first layer includes a photoelectric conversion device; the second layer includes a first and a second circuit; the third layer includes a third and a fourth circuit; the first circuit and the photoelectric conversion device have a function of generating imaging data; the third circuit has a function of reading the imaging data; the second circuit has a function of storing the imaging data read by the third circuit; the fourth circuit has a function of reading the imaging data stored in the second circuit; and the first circuit and the second circuit include a transistor including a metal oxide in a channel formation region.