公开(公告)号：US20240373709A1

公开(公告)日：2024-11-07

申请号：US18688811

申请日：2022-08-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Takanori MATSUZAKI ,  Munehiro KOZUMA

IPC: H10K59/131 ,  H01L27/12 ,  H10K50/19 ,  H10K59/121

Abstract: An object is to provide a semiconductor device in which the number of control wirings is reduced. In a semiconductor device of one embodiment of the present invention, a first wiring (GLa) is connected to a first input terminal (54a) of a logic circuit (54) and a gate of a sixth transistor (M6); a second wiring (GLb) is connected to a second input terminal (54b) of the logic circuit (54), a gate of the third transistor (M3), a gate of the fourth transistor (M4), and a gate of the fifth transistor (M5); a gate of the first transistor (M1) is connected to an output terminal (54y) of the logic circuit (54); and the logic circuit (54) has a function of outputting a signal obtained by a logic operation of a signal input to the first input terminal (54a) and a signal input to the second input terminal (54b) to the output terminal (54y).

公开(公告)号：US20230352477A1

公开(公告)日：2023-11-02

申请号：US18016880

申请日：2021-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Yuki OKAMOTO ,  Takayuki IKEDA

IPC: H01L27/06 ,  H01L29/786 ,  G06F7/544 ,  H01L27/092 ,  G06N3/065

CPC classification number: H01L27/0688 ,  H01L29/7869 ,  G06F7/5443 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0924 ,  G06N3/065

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. The analog calculator, the first memory circuit, and the second memory circuit each include a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data to the digital calculator as digital data. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data to the analog calculator as analog data. The analog calculator has a function of performing product-sum operation using the second weight data. The amount of current flowing between a source and a drain of at least one of the transistors each including the oxide semiconductor in the channel formation region in the analog calculator and the second memory circuit is the amount of current flowing when the transistor operates in a subthreshold region.

公开(公告)号：US20230099168A1

公开(公告)日：2023-03-30

申请号：US17802281

申请日：2021-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H10B12/00 ,  H01L29/786

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

公开(公告)号：US20230049977A1

公开(公告)日：2023-02-16

申请号：US17785510

申请日：2020-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takuro KANEMURA

IPC: G06N3/063 ,  G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G06F7/544

Abstract: A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

公开(公告)号：US20220077705A1

公开(公告)日：2022-03-10

申请号：US17417482

申请日：2019-12-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Takayuki IKEDA ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Takahiko ISHIZU ,  Takeshi AOKI

IPC: H02J7/00

Abstract: A secondary battery deteriorates due to repeated charging and discharging, which leads to a decrease in a battery voltage and a battery capacity. The lifetime of a secondary battery is prolonged by preventing charging at an excessive charging value that would be caused by deterioration of the secondary battery. By performing charge control in consideration of the degree of deterioration of a secondary battery, a longer lifetime of a secondary battery can be achieved. In charging a secondary battery, a charge control circuit controls a current value to a preset value, and a charging current control circuit (specifically a circuit including an error amplifier) included in a protection circuit determines a current value supplied to the secondary battery. That is, the current value supplied to the secondary battery is controlled by both the charge control circuit and the charging current control circuit that is a part of the protection circuit.

公开(公告)号：US20220020793A1

公开(公告)日：2022-01-20

申请号：US17490009

申请日：2021-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L27/146 ,  H01L29/786 ,  H01L31/105 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US20210384753A1

公开(公告)日：2021-12-09

申请号：US17283689

申请日：2019-10-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Takayuki IKEDA ,  Takanori MATSUZAKI ,  Kei TAKAHASHI ,  Mayumi MIKAMI ,  Shunpei YAMAZAKI

IPC: H02J7/00 ,  G11C11/401 ,  H01M10/48 ,  H01M10/42 ,  H01M10/613 ,  H01M10/615 ,  H01M10/633 ,  H01M10/625 ,  H01M10/0525

Abstract: The safety is ensured in such a manner that with an abnormality detection system of a secondary battery, abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early, and a user is warned or the use of the secondary battery is stopped. The abnormality detection system of the secondary battery determines whether the temperature of the secondary battery is within a temperature range in which normal operation can be performed on the basis of temperature data obtained with a temperature sensor. In the case where the temperature of the secondary battery is high, a cooling device is driven by a control signal from the abnormality detection system of the secondary battery. The abnormality detection system of the secondary battery includes at least a memory means. The memory means has a function of holding an analog signal and includes a transistor using an oxide semiconductor for a semiconductor layer.

公开(公告)号：US20190229216A1

公开(公告)日：2019-07-25

申请号：US16375135

申请日：2019-04-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takashi NAKAGAWA ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA

IPC: H01L29/786 ,  H03K19/177 ,  H03K19/00 ,  H01L27/28 ,  H01L29/16 ,  H01L27/12 ,  H01L29/24

Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.

公开(公告)号：US20180109752A1

公开(公告)日：2018-04-19

申请号：US15729169

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Munehiro KOZUMA ,  Yoshiyuki KUROKAWA

IPC: H04N5/455 ,  H03M99/00

CPC classification number: H04N5/455 ,  G11C14/0072 ,  H03M99/00 ,  H04H40/00 ,  H04N21/442

Abstract: A decoder with reduced power consumption is provided. The decoder includes a first circuit and a second circuit for holding data. The second circuit includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor include an oxide semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor. The decoder is configured to provide or stop power supply to the semiconductor device depending on a packet ID of a header portion of the data and to perform data storing or restoring of data between the first circuit and the second circuit.

公开(公告)号：US20150341035A1

公开(公告)日：2015-11-26

申请号：US14725308

申请日：2015-05-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Takeshi AOKI

IPC: H03K19/0944 ,  H01L29/24 ,  H01L27/12 ,  H03K19/177 ,  H01L29/786

CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/1776

Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

Abstract translation: 可编程逻辑器件包括多个可编程逻辑元件（PLE），其电连接由第一配置数据控制。 每个PLE包括LUT，其中输入信号的逻辑电平和输出信号的逻辑电平之间的关系由第二配置数据确定，输入LUT的输出信号的FF和MUX 。 MUX包括至少两个开关，每个开关包括第一和第二晶体管。 包括第三配置数据的信号通过第一晶体管输入到第二晶体管的栅极。 LUT的输出信号或FF的输出信号被输入到第二晶体管的源极和漏极之一。