公开(公告)号：US20150123126A1

公开(公告)日：2015-05-07

申请号：US14594991

申请日：2015-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Keisuke MURAYAMA

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/7831

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

Abstract translation: 晶体管包括通过介于第一栅极电极层和氧化物半导体层叠层之间的绝缘层在第一栅极电极层和第二栅极电极层之间的氧化物半导体堆叠层和介于第二栅极电极层和氧化物之间的绝缘层 半导体堆叠层。 沟道形成区域的厚度小于氧化物半导体堆叠层中的其它区域。 此外，在该晶体管中，栅电极层之一被设置为所谓的用于控制阈值电压的背栅。 控制施加到背栅的电位使得能够控制晶体管的阈值电压，这使得容易维持晶体管的常关特性。

公开(公告)号：US20140326991A1

公开(公告)日：2014-11-06

申请号：US14258466

申请日：2014-04-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke MATSUBAYASHI ,  Toshimitsu OBONAI ,  Noritaka ISHIHARA ,  Shunpei YAMAZAKI

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: A semiconductor device in which variation in electrical characteristics between transistors is reduced is provided. A transistor where a channel is formed in an oxide semiconductor layer is included, and a concentration of carriers contained in a region where the channel is formed in the oxide semiconductor layer is lower than or equal to 1×1015/cm3, preferably lower than or equal to 1×1013/cm3, more preferably lower than or equal to 1×1011/cm3, whereby an energy barrier height which electrons flowing between a source and a drain should go over converges at a constant value. In this manner, a semiconductor device in which variation in the electrical characteristics between the transistors is inhibited is provided.

Abstract translation: 提供一种减小晶体管之间的电特性变化的半导体器件。 包括在氧化物半导体层中形成沟道的晶体管，并且在氧化物半导体层中形成沟道的区域中所含的载流子浓度低于或等于1×1015 / cm3，优选低于或等于 等于1×10 13 / cm 3，更优选低于或等于1×10 11 / cm 3，由此在源极和漏极之间流动的电子的能量势垒高度会以恒定值收敛。 以这种方式，提供了其中抑制晶体管之间的电特性的变化的半导体器件。

公开(公告)号：US20140203276A1

公开(公告)日：2014-07-24

申请号：US14154483

申请日：2014-01-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Hirokazu WATANABE

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1222 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device. The semiconductor device includes a first oxide layer over an insulating film; an oxide semiconductor layer over the first oxide layer; a gate insulating film over the oxide semiconductor layer; and a gate electrode over the gate insulating film. The first oxide layer contains indium. The oxide semiconductor layer contains indium and includes a channel formation region. The distance from the interface to the channel formation region is 20 nm or more, preferably 30 nm or more, further preferably 40 nm or more, still further preferably 60 nm or more.

Abstract translation: 提供高度可靠的半导体器件。 半导体器件包括绝缘膜上的第一氧化物层; 在所述第一氧化物层上的氧化物半导体层; 氧化物半导体层上的栅极绝缘膜; 以及栅极绝缘膜上的栅电极。 第一氧化物层含有铟。 氧化物半导体层含有铟，并且包括沟道形成区域。 从界面到沟道形成区域的距离为20nm以上，优选为30nm以上，进一步优选为40nm以上，进一步优选为60nm以上。

公开(公告)号：US20220328694A1

公开(公告)日：2022-10-13

申请号：US17844767

申请日：2022-06-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuya HANAOKA ,  Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI ,  Shunpei YAMAZAKI ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L29/417

Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.

公开(公告)号：US20220037373A1

公开(公告)日：2022-02-03

申请号：US17500020

申请日：2021-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Keisuke MURAYAMA

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

公开(公告)号：US20210234025A1

公开(公告)日：2021-07-29

申请号：US17227450

申请日：2021-04-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Yukinori SHIMA ,  Hajime TOKUNAGA ,  Toshinari SASAKI ,  Keisuke MURAYAMA ,  Daisuke MATSUBAYASHI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L29/786 ,  H01L27/12

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

公开(公告)号：US20210036159A1

公开(公告)日：2021-02-04

申请号：US17065635

申请日：2020-10-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Keisuke MURAYAMA

IPC: H01L29/786 ,  H01L29/78

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

公开(公告)号：US20200227566A1

公开(公告)日：2020-07-16

申请号：US16833918

申请日：2020-03-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Hirokazu WATANABE ,  Yuhei SATO ,  Yasumasa YAMANE ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US20200220028A1

公开(公告)日：2020-07-09

申请号：US16821433

申请日：2020-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Yutaka OKAZAKI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04 ,  H01L29/49

Abstract: A transistor in which a short-channel effect is not substantially caused and which has switching characteristics even in the case where the channel length is short is provided. Further, a highly integrated semiconductor device including the transistor is provided. A short-channel effect which is caused in a transistor including silicon is not substantially caused in the transistor including an oxide semiconductor film. The channel length of the transistor including the oxide semiconductor film is greater than or equal to 5 nm and less than 60 nm, and the channel width thereof is greater than or equal to 5 nm and less than 200 nm. At this time, the channel width is made 0.5 to 10 times as large as the channel length.

公开(公告)号：US20190139783A1

公开(公告)日：2019-05-09

申请号：US16093268

申请日：2017-04-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kazutaka KURIKI ,  Yuji EGI ,  Noritaka ISHIHARA ,  Yusuke NONAKA ,  Yasumasa YAMANE ,  Ryo TOKUMARU ,  Daisuke MATSUBAYASHI

IPC: H01L21/4757 ,  H01L27/105 ,  H01L27/12 ,  H01L29/66 ,  H01L21/443 ,  H01L21/477 ,  H01L21/02 ,  H01L29/786 ,  H01J37/32

Abstract: A semiconductor device having high reliability is provided.A first conductor is formed, a first insulator is formed over the first conductor, a second insulator is formed over the first insulator, a third insulator is formed over the second insulator, microwave-excited plasma treatment is performed on the third insulator, an island-shaped first oxide semiconductor is formed over the third insulator and a second conductor and a third conductor are formed over the first oxide semiconductor, an oxide semiconductor film is formed over the first oxide semiconductor, the second conductor, and the third conductor, a first insulating film is formed over the oxide semiconductor film, a conductive film is formed over the first insulating film, a fourth insulator and a fourth conductor are formed by partly removing the first insulating film and the conductive film, a second insulating film is formed to cover the oxide semiconductor film, the fourth insulator, and the fourth conductor, a second oxide semiconductor and a fifth insulator are formed by partly removing the oxide semiconductor film and the second insulating film to expose a side surface of the first oxide semiconductor, a sixth insulator is formed in contact with the side surface of the first oxide semiconductor and a side surface of the second oxide semiconductor, a seventh insulator is formed in contact with the sixth insulator, and heat treatment is performed.