公开(公告)号：US20240274696A1

公开(公告)日：2024-08-15

申请号：US18606052

申请日：2024-03-15

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Masashi TSUBUKU

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L27/12 ,  H01L27/146 ,  H01L29/786

CPC分类号： H01L29/66969 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/14616 ,  H01L27/14689 ,  H01L29/7869 ,  H01L29/78696

摘要： The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US20240105853A1

公开(公告)日：2024-03-28

申请号：US18524033

申请日：2023-11-30

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/7869 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78648

摘要： A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

公开(公告)号：US20230335646A1

公开(公告)日：2023-10-19

申请号：US18211652

申请日：2023-06-20

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Hirokazu WATANABE ,  Yuhei SATO ,  Yasumasa YAMANE ,  Daisuke MATSUBAYASHI

IPC分类号： H01L29/786 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/78618 ,  H01L29/7869 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78696

摘要： A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US20220123148A1

公开(公告)日：2022-04-21

申请号：US17563238

申请日：2021-12-28

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L29/51

摘要： A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

公开(公告)号：US20210408298A1

公开(公告)日：2021-12-30

申请号：US17295693

申请日：2019-11-19

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Erika TAKAHASHI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC分类号： H01L29/786

摘要： A semiconductor device with high reliability is provided. A first conductor and a second conductor are provided over and in contact with a first oxide. A first insulator is provided to cover the first oxide, a first conductor, and a second conductor. The first insulator includes an opening portion. The first oxide is exposed on a bottom surface of the opening portion. A side surface of the first conductor and a side surface of the second conductor are exposed on a side surface of the opening portion. A second oxide is provided in contact with the first oxide, the side surface of the first conductor, and the second conductor in the opening portion. A second insulator is provided in the opening portion with the second oxide therebetween. A third conductor is provided in the opening portion with the second insulator therebetween. Lower end portions of the side surface of the first conductor and the second conductor touch an ellipse or a circle with a center above the first oxide.

公开(公告)号：US20170186858A1

公开(公告)日：2017-06-29

申请号：US15461575

申请日：2017-03-17

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Masashi TSUBUKU

IPC分类号： H01L29/66 ,  H01L27/146 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

CPC分类号： H01L29/66969 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/14616 ,  H01L27/14689 ,  H01L29/7869 ,  H01L29/78696

摘要： The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US20170077313A1

公开(公告)日：2017-03-16

申请号：US15246927

申请日：2016-08-25

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Hideomi SUZAWA

IPC分类号： H01L29/786 ,  H01L29/24 ,  H01L27/146 ,  H01L27/105 ,  H01L27/12 ,  H01L29/04 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/7869 ,  H01L29/78693

摘要： A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

摘要翻译： 提供具有能够防止由于小型化引起的电特性降低的结构的半导体器件。 半导体器件在绝缘表面上包括其中顺序形成第一氧化物半导体层和第二氧化物半导体层的堆叠，以及覆盖堆叠表面的一部分的第三氧化物半导体层。 第三氧化物半导体层包括与堆叠接触的第一层和在第一层上的第二层。 第一层包括微晶层，第二层包括其中c轴在垂直于第一层的表面的方向上排列的结晶层。

公开(公告)号：US20160240684A1

公开(公告)日：2016-08-18

申请号：US15019004

申请日：2016-02-09

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Yoshinobu ASAMI ,  Yutaka OKAZAKI ,  Motomu KURATA ,  Katsuaki TOCHIBAYASHI ,  Shinya SASAGAWA ,  Kensuke YOSHIZUMI ,  Hideomi SUZAWA

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L21/465 ,  H01L21/47 ,  H01L29/66 ,  H01L21/4757

CPC分类号： H01L29/7869 ,  H01L21/47 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78648 ,  H01L33/00

摘要： A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

摘要翻译： 提供一种小型化晶体管，具有低寄生电容的晶体管，具有高频特性的晶体管，或包括晶体管的半导体器件。 半导体器件包括第一绝缘体，第一绝缘体上的氧化物半导体，与氧化物半导体接触的第一导体和第二导体，位于第一和第二导体之上并具有到达氧化物的开口的第二绝缘体 半导体，氧化物半导体上的第三绝缘体和第二绝缘体，以及位于第三绝缘体上的第四导体。 第一导体包括第一区域和第二区域。 第二导体包括第三区域和第四区域。 第二区域面对具有第一导体的第三区域，并且第一区域之间插入第一绝缘体。 第二区域比第一区域薄。 第三区域比第四区域薄。

公开(公告)号：US20150333160A1

公开(公告)日：2015-11-19

申请号：US14813413

申请日：2015-07-30

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC分类号： H01L29/66 ,  H01L29/45 ,  H01L21/4763 ,  H01L21/441 ,  H01L21/4757 ,  H01L29/786

CPC分类号： H01L21/02565 ,  C23C14/086 ,  C23C14/3414 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47576 ,  H01L21/47635 ,  H01L29/045 ,  H01L29/26 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

摘要： In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.

摘要翻译： 在氧化物半导体层中包括沟道形成区域的半导体器件中，使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触并与氧化物半导体层接触的栅极绝缘膜供给氧 通过离子注入法引入的栅极绝缘膜到氧化物半导体层。

公开(公告)号：US20150060846A1

公开(公告)日：2015-03-05

申请号：US14471766

申请日：2014-08-28

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC分类号： H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L29/51

CPC分类号： H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

摘要： A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

摘要翻译： 提供其中调整阈值的半导体器件。 在包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极和半导体之间的电子捕获层的晶体管中，电子捕获层包括结晶的氧化铪。 通过使用氧化铪作为靶的溅射法沉积结晶的氧化铪。 溅射法中，衬底温度为Tsub（℃），气氛中氧的比例为P（％）时，P≥45〜0.15×Tsub。 结晶的氧化铪具有优异的电子捕获性能。 通过适当数量的电子的陷阱，可以调整半导体器件的阈值。