公开(公告)号：US20150236166A1

公开(公告)日：2015-08-20

申请号：US14700528

申请日：2015-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Tetsuhiro TANAKA ,  Junichi KOEZUKA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

Abstract translation: 提供了一种具有稳定和高电特性并且高产率的小型化晶体管。 在包括依次层叠有氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管的半导体装置中，设置与栅电极层的侧面接触的第一侧壁绝缘层， 提供第二侧壁绝缘层以覆盖第一侧壁绝缘层的侧表面。 第一侧壁绝缘层是在其侧表面上形成具有均匀形状的缝隙的氧化铝膜。 第二侧壁绝缘层设置成覆盖缝隙。 源电极层和漏电极层设置成与氧化物半导体膜和第二侧壁绝缘层接触。

公开(公告)号：US20140179058A1

公开(公告)日：2014-06-26

申请号：US14191853

申请日：2014-02-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Shunichi ITO ,  Miyuki HOSOBA

IPC: H01L29/66

CPC classification number: H01L29/66969 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/7869

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract translation: 本发明的目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。在包括通道蚀刻的半导体器件的制造方法中 倒置交错薄膜晶体管，氧化物半导体膜和导电膜使用掩模层进行蚀刻，该掩模层使用作为透光的多色调掩模形成，该透光掩模通过该曝光掩模透射，以便具有多个 强度 在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。