公开(公告)号：US6136646A

公开(公告)日：2000-10-24

申请号：US328755

申请日：1999-06-09

申请人： Kung Linliu ,  Wan-Yih Lien

发明人： Kung Linliu ,  Wan-Yih Lien

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10814 ,  H01L27/10888 ,  H01L28/84 ,  H01L28/91

摘要： A method for manufacturing dynamic random access memory (DRAM) capacitor. A first insulation layer having a plurality of first plugs and second plugs therein is formed over a substrate. A plurality of bit lines is formed over the first insulation layer. Each bit line has a multiple of bit line contacts, and each bit line contact is connected electrically to one of the first plugs. A cap layer is formed on top of the bit lines and spacers are formed on the sidewalls of the bit lines. The spacers are formed in such a way that they are linked near the bit line contact of every pair of neighboring bit lines. A planarized second insulation layer is formed over the substrate. Using the cap layers, the spacers and the second plugs as stopping points, an etching operation is carried out to form the lower electrode openings of capacitors and node contact openings. A conformal conductive layer that covers the exposed surfaces of the electrode openings and the node contact openings are formed, hence forming the lower electrode of a capacitor. A dielectric layer is formed over the lower electrode, and finally an upper electrode is formed over the dielectric layer to form a complete capacitor.

摘要翻译： 一种用于制造动态随机存取存储器（DRAM）电容器的方法。 在衬底上形成有多个第一插塞和第二插头的第一绝缘层。 多个位线形成在第一绝缘层上。 每个位线具有多个位线触点，并且每个位线触点电连接到第一插头之一。 在位线的顶部形成盖层，并且在位线的侧壁上形成间隔物。 间隔件以这样的方式形成，使得它们被连接在每对相邻位线的位线接触附近。 平面化的第二绝缘层形成在衬底上。 使用盖层，间隔件和第二塞作为停止点，进行蚀刻操作以形成电容器和节点接触开口的下电极开口。 形成覆盖电极开口和节点接触开口的暴露表面的保形导电层，从而形成电容器的下电极。 在下电极上形成介电层，最后在电介质层上形成上电极以形成完整的电容器。

公开(公告)号：US6103623A

公开(公告)日：2000-08-15

申请号：US166733

申请日：1998-10-05

申请人： Wan-Yih Lien ,  Yi-Ping Lee

发明人： Wan-Yih Lien ,  Yi-Ping Lee

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L23/53214 ,  H01L21/76838 ,  H01L23/53257 ,  H01L2924/0002

摘要： A process for forming a tungsten plug structure, in a contact hole, without recessing of the tungsten plug, or of the adhesive and barrier layers, located on the sides of the contact hole, during the tungsten plug patterning procedure, has been developed. The process features a two stage, in situ RIE procedure, in which a photoresist shape, larger in width than the diameter of the contact hole, is used as a mask to allow patterning of an aluminum based layer, of an underlying tungsten, and of the barrier and adhesive layers. The result of the two stage, in situ RIE procedure is an aluminum based interconnect structure, overlying a tungsten plug structure, with the tungsten plug structure comprised of a tungsten plug, in a contact hole, protected during the patterning procedure by the overlying aluminum based interconnect structure.

摘要翻译： 已经开发了一种用于在钨插件图案化步骤期间在接触孔中形成钨插塞结构而不会使钨插塞或位于接触孔侧面上的粘合剂层和阻挡层凹陷的方法。 该方法具有两级原位RIE方法，其中使用宽度大于接触孔直径的光致抗蚀剂形状作为掩模，以允许图案化铝基层，下层钨和 屏障和粘合层。 两级原位RIE程序的结果是铝基互连结构，覆盖钨插塞结构，钨插塞结构由钨插塞组成，在接触孔中，在图案化过程中由上覆的铝基 互连结构。

公开(公告)号：US6074952A

公开(公告)日：2000-06-13

申请号：US74341

申请日：1998-05-07

申请人： Hao-Chieh Liu ,  Erik S. Jeng ,  Bi-Ling Chen ,  Wan-Yih Lien

发明人： Hao-Chieh Liu ,  Erik S. Jeng ,  Bi-Ling Chen ,  Wan-Yih Lien

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/306

CPC分类号： H01L27/10894 ,  H01L21/31116 ,  H01L21/76816 ,  H01L27/10882

摘要： A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.

摘要翻译： 在半导体晶片中形成多个接触孔70的方法使用一个步骤。 半导体晶片包括覆盖硅衬底51的电介质层69，氮化硅层67a和氮氧化硅层63c。 首先，在电介质层上显影光致抗蚀剂68层。 在形成电介质层之前，形成氮氧化硅层，覆盖第一导电层，并且氮化硅层形成在第二导电层上。 其次，进行蚀刻步骤以蚀刻穿过氧氮化硅层，氮化硅层，氧氮化硅层上方的电介质层的一部分和氮化硅层，以暴露硅衬底51，第一导电层63a， 和第二导电层67c。 该蚀刻配方包括第一化学和第二化学。 第一种化学性质包括C2F6，C4F8，CH3F和Ar。 第二化学选自包括O 2，CO 2，CO及其任何组合的组。 因此，在硅衬底，第一导电层和第二导电层上形成多个接触孔。