公开(公告)号：US08303087B2

公开(公告)日：2012-11-06

申请号：US13050206

申请日：2011-03-17

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： B41J2/14

CPC分类号： B41J2/1603 ,  B41J2/162 ,  B41J2/1623 ,  Y10T29/49401

摘要： The present invention discloses a package structure of an inkjet-printhead chip. The structure includes: a nozzle structure of a print element including an ink chamber layer, a nozzle base layer on the ink chamber layer, and a nozzle layer on the nozzle base layer, wherein a plurality of nozzle through holes are set in the nozzle layer and pass through an ink chamber of the ink chamber layer; a flexible substrate set on the nozzle layer, wherein there is at least an opening set in the flexible substrate to expose those nozzle through holes; and a chip set under the ink chamber layer. Besides, the present package method is to utilize the micro-manufacturing process to form the nozzle structure of a print element and the tape automatic bonding process to bond the flexible substrate on the nozzle layer and the chip under the ink chamber layer.

摘要翻译： 本发明公开了一种喷墨打印头芯片的封装结构。 该结构包括：包括墨室层的印刷元件的喷嘴结构，墨室层上的喷嘴基层和喷嘴基层上的喷嘴层，其中在喷嘴层中设置多个喷嘴通孔 并通过墨室层的墨室; 设置在喷嘴层上的柔性基板，其中在柔性基板中至少设有一个开口，以暴露出这些喷嘴通孔; 以及设置在墨室层下面的芯片。 此外，本发明的包装方法是利用微制造工艺形成印刷元件的喷嘴结构和胶带自动粘合工艺，以将柔性基材粘合在喷嘴层和墨水室层下方的芯片上。

公开(公告)号：US06287957B1

公开(公告)日：2001-09-11

申请号：US09468196

申请日：1999-12-21

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： H01L214763

CPC分类号： H01L21/76897

摘要： The present invention discloses a method for forming a self-aligned contact hole, which provides a large process window and ensures full utilization of bottom contact area even when the overlay is not well aligned. The method comprises the steps of (a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon; (b) forming a conformal layer of etch barrier material overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode; (c) forming an insulating layer overlying the barrier layer; (d) forming a mask layer overlying the insulating layer; (e) etching an opening through the mask layer and part of the way through the insulating layer, aligned with the diffusion region, until the barrier layer is exposed; (f) forming spacers on the sidewalls of the opening; (g) removing the remaining portion of the insulating layer underneath the opening by isotropically etching using mask layer, spacers and barrier layer as stopping layers; and (h) removing the barrier layer underneath the opening, thereby exposing the diffusion region.

摘要翻译： 本发明公开了一种用于形成自对准接触孔的方法，其提供了大的工艺窗口，并且确保了底部接触面积的充分利用，即使当覆盖层不能很好对准时。 该方法包括以下步骤：（a）提供其上具有栅电极和扩散区的半导体衬底; （b）形成覆盖在包括所述扩散区域和所述栅电极的所述上表面和所述侧壁的所述衬底表面上的蚀刻阻挡材料的共形层; （c）形成覆盖在阻挡层上的绝缘层; （d）形成覆盖绝缘层的掩模层; （e）蚀刻通过掩模层的开口和通过与扩散区对准的绝缘层的一部分，直到暴露阻挡层; （f）在开口的侧壁上形成间隔物; （g）通过使用掩模层，间隔物和阻挡层作为停止层进行各向同性蚀刻，去除开口下方的绝缘层的剩余部分; 和（h）去除开口下方的阻挡层，从而暴露扩散区域。

公开(公告)号：US06263586B1

公开(公告)日：2001-07-24

申请号：US09350964

申请日：1999-07-09

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： F26B508

CPC分类号： H01L21/67092

摘要： A device and method for planarizing a film layer device on a silicon wafer. The device has a circular track whose surface faces the track center, a carrier capable of moving along the track and carrying wafers around with their front surfaces facing the center, and a set of heating elements for heating the film layers on the wafers to make them fluid. Utilizing the centrifugal force on the film layer generated by the circular movement and the fluidity of the film layer provided by heating, planarization of the film layer is achieved.

摘要翻译： 一种用于在硅晶片上平坦化膜层器件的器件和方法。 该装置具有表面面向轨道中心的圆形轨道，能够沿着轨道移动并且以其前表面面向中心携带晶片的载体，以及用于加热晶片上的膜层的一组加热元件，以使它们 流体。 利用通过圆周运动产生的膜层上的离心力和通过加热提供的膜层的流动性，实现了膜层的平坦化。

公开(公告)号：US6165909A

公开(公告)日：2000-12-26

申请号：US306095

申请日：1999-05-06

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： H01L21/02 ,  H01L21/302

CPC分类号： H01L28/92

摘要： A method for fabricating a capacitor is described. A dielectric layer and a polysilicon layer thereon are provided. A patterned oxide layer and spacers on the sidewalls of the patterned oxide layer are formed. The polysilicon layer is etched using the oxide layer and spacer as an etching mask. The oxide layer and spacer are then removed. A dielectric layer and a conductive layer are sequentially formed on the polysilicon layer.

摘要翻译： 描述制造电容器的方法。 提供介电层和其上的多晶硅层。 形成图案化氧化物层和图案化氧化物层的侧壁上的间隔物。 使用氧化物层和间隔物作为蚀刻掩模蚀刻多晶硅层。 然后除去氧化物层和间隔物。 介电层和导电层依次形成在多晶硅层上。

公开(公告)号：US6033966A

公开(公告)日：2000-03-07

申请号：US189066

申请日：1998-11-09

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/92 ,  H01L27/10852

摘要： A method for manufacturing an 8-shaped bottom storage node. A dielectric layer and a polysilicon layer are deposited. A bit line contact and a storage node contact are formed through the dielectric layer and the polysilicon layer down to an access transistor. After formation of the bit line contact and the storage node contact, the polysilicon layer is removed leaving the first dielectric layer. A polysilicon layer is deposited over the dielectric layer and into the bit line contact and storage node contacts. This is followed by a deposition of a tungsten silicide layer and a second dielectric layer. These layers are then etched to form a bit line above the bit line contact. Sidewall spacers are formed on the sidewalls of the bit line. Another polysilicon layer is deposited into the storage node contacts and above the bit line. This polysilicon layer is patterned and etched in an 8 pattern. Oxide spacers are formed on the sidewalls of the etched polysilicon layer. Next, using the oxide spacers and oxide as a hard mask, the polysilicon layer is etched until the top of the bit line is reached. Finally, the oxide spacers are removed and an 8 shaped storage node is formed.

摘要翻译： 一种用于制造8形底部存储节点的方法。 沉积介质层和多晶硅层。 通过电介质层和多晶硅层形成位线接触和存储节点接触，直至存取晶体管。 在形成位线接触和存储节点接触之后，去除离开第一电介质层的多晶硅层。 多晶硅层沉积在电介质层上并进入位线接触和存储节点接触。 之后是硅化钨层和第二介电层的沉积。 然后蚀刻这些层以在位线接触之上形成位线。 侧壁间隔件形成在位线的侧壁上。 另一个多晶硅层沉积到存储节点触点中并位于位线之上。 将该多晶硅层图案化并以8图案蚀刻。 在蚀刻的多晶硅层的侧壁上形成氧化物间隔物。 接下来，使用氧化物间隔物和氧化物作为硬掩模，蚀刻多晶硅层直到达到位线的顶部。 最后，去除氧化物间隔物并形成8个形状的储存节点。

公开(公告)号：US20080117256A1

公开(公告)日：2008-05-22

申请号：US11600018

申请日：2006-11-16

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： B41J2/16

CPC分类号： B41J2/1603 ,  B41J2/162 ,  B41J2/1623 ,  Y10T29/49401

摘要： The present invention discloses a package method of the inkjet-printhead chip and its structure. The structure includes: a nozzle structure of a print element including an ink chamber layer and a nozzle layer on the ink chamber layer, wherein a plurality of nozzle through holes are set in the nozzle layer and pass through an ink chamber of the ink chamber layer; a flexible substrate set on the nozzle layer, wherein there is at least an opening set in the flexible substrate to expose those nozzle through holes; and a chip set under the ink chamber layer. Besides, the present package method is to utilize the micro-manufacturing process to form the nozzle structure of a print element and the tape automatic bonding process to bond the flexible substrate on the nozzle layer and the chip under the ink chamber layer.

摘要翻译： 本发明公开了一种喷墨打印头芯片的封装方法及其结构。 该结构包括：印刷元件的喷嘴结构，包括墨室层和墨室层上的喷嘴层，其中多个喷嘴通孔设置在喷嘴层中并通过墨室层的墨室 ; 设置在喷嘴层上的柔性基板，其中在柔性基板中至少设有一个开口，以暴露出这些喷嘴通孔; 以及设置在墨室层下面的芯片。 此外，本发明的包装方法是利用微制造工艺形成印刷元件的喷嘴结构和胶带自动粘合工艺，以将柔性基材粘合在喷嘴层和墨水室层下方的芯片上。

公开(公告)号：US06133085A

公开(公告)日：2000-10-17

申请号：US346324

申请日：1999-07-02

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/82 ,  H01L28/86 ,  H01L27/10852

摘要： A method of forming a bottom storage node of a DRAM capacitor over a contact plug is disclosed. The method comprises the steps of: depositing an oxide layer over the contact plug; etching the oxide layer using a first photoresist layer having with a first masking pattern, the first masking pattern allowing the removal of the oxide layer over the contact plug; depositing a polysilicon layer over the oxide layer and in electrical contact with the contact plug; forming a second photoresist layer having a second masking pattern onto the polysilicon layer, the second masking pattern being substantially similar to the first masking pattern, but rotated by a predetermined angle; and etching the polysilicon layer in accordance with the second photoresist layer until the oxide layer is reached.

摘要翻译： 公开了一种在触点插头上形成DRAM电容器的底部存储节点的方法。 该方法包括以下步骤：在接触插塞上沉积氧化物层; 使用具有第一掩模图案的第一光致抗蚀剂层蚀刻氧化物层，第一掩模图案允许在接触插塞上去除氧化物层; 在所述氧化物层上沉积多晶硅层并与所述接触插塞电接触; 在所述多晶硅层上形成具有第二掩模图案的第二光致抗蚀剂层，所述第二掩模图案基本上类似于所述第一掩模图案，但旋转预定角度; 并根据第二光致抗蚀剂层蚀刻多晶硅层直到达到氧化物层。

公开(公告)号：US6110837A

公开(公告)日：2000-08-29

申请号：US301481

申请日：1999-04-28

申请人： Kung Linliu ,  Bor-Wen Chan

发明人： Kung Linliu ,  Bor-Wen Chan

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/00

CPC分类号： H01L21/0274 ,  H01L21/0337 ,  H01L21/0338

摘要： The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.

摘要翻译： 本发明公开了一种在基板上形成半临界尺寸的硬掩模的方法。 为集成电路的基底提供基板。 在基板上形成氧化硅层。 在氧化硅层上形成光致抗蚀剂层，其具有常规光刻工艺可制造的临界尺寸。 随后，通过使用光致抗蚀剂层作为蚀刻掩模，在氧化硅层中形成半临界尺寸的硬掩模。 在形成氧化物硬掩模之后，通过使用氧化物硬掩模形成半临界尺寸的栅极结构。

公开(公告)号：US06096653A

公开(公告)日：2000-08-01

申请号：US206780

申请日：1998-12-07

申请人： Yeur-Luen Tu ,  Kung Linliu

发明人： Yeur-Luen Tu ,  Kung Linliu

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76819 ,  H01L21/76885 ,  H01L21/32139

摘要： A method for forming a metal interconnect structure over a high topography dielectric is disclosed. The method comprises the steps of: depositing a conductive layer over the high topography dielectric layer; depositing a planarized oxide layer over the conducting layer, patterning and etching the planarized oxide layer in accordance with a desired metal interconnect pattern using the conducting layer as an etching stop; using the planarized oxide layer as a hard mask, etching the conducting layer in accordance with the desired metal interconnect pattern imparted onto the planarized oxide layer; and depositing a gap-filling oxide layer over the planarized oxide layer and the high topography dielectric layer.

摘要翻译： 公开了一种在高地形电介质上形成金属互连结构的方法。 该方法包括以下步骤：在高地形电介质层上沉积导电层; 在所述导电层上沉积平坦化的氧化物层，使用所述导电层作为蚀刻停止器，根据期望的金属互连图案图案化和蚀刻所述平坦化的氧化物层; 使用平坦化氧化物层作为硬掩模，根据施加到平坦化氧化物层上的所需金属互连图案来蚀刻导电层; 以及在所述平坦化氧化物层和所述高形貌介电层上沉积间隙填充氧化物层。

公开(公告)号：US6037217A

公开(公告)日：2000-03-14

申请号：US250372

申请日：1999-02-16

申请人： Kung Linliu

发明人： Kung Linliu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An integrated circuit (IC) fabrication method is provided for the fabrication of an electrode structure having an increased surface area for a double-crown type of capacitor in a dynamic random-access memory (DRAM) device. In this method, damascene technology is used, which can help reduce the height difference between the memory cell region and the peripheral region, thus eliminating the required planarization process in the prior art. Moreover, this method can provide an electrode structure having a large surface area that allows the associated capacitor to be considerably increased in capacitance as compared to the prior art while requiring no increase in the layout area in the integrated circuit.

摘要翻译： 提供了一种用于制造在动态随机存取存储器（DRAM）装置中双冠型电容器具有增加的表面面积的电极结构的集成电路（IC）制造方法。 在这种方法中，使用大马士革技术，这可以有助于降低存储单元区域和周边区域之间的高度差，从而消除现有技术中所需的平面化处理。 此外，该方法可以提供具有大表面积的电极结构，其允许相关电容器与现有技术相比显着增加电容，同时不需要增加集成电路中的布局面积。