公开(公告)号：US20170092375A1

公开(公告)日：2017-03-30

申请号：US15003315

申请日：2016-01-21

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd. ,  Tianma Micro-Electronics Co., Ltd.

Inventor： Zhiqiang Xia ,  Dongliang Dun ,  Huijun Jin

IPC: G11C19/28 ,  G09G3/36 ,  G11C5/14

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2320/0214 ,  G09G2330/021 ,  G11C5/147 ,  G11C29/32

Abstract: A shift register, a driving method thereof, and a gate driving circuit. The shift register includes a first transistor, with a control terminal thereof electrically connected to a first control node; a scan driving unit; a reset unit; a maintaining control unit; a first potential maintaining unit, with a control terminal thereof electrically connected to a second control node, an input terminal thereof electrically connected to a third level signal line, and an output terminal thereof electrically connected to the first control node; and a second potential maintaining unit, with a first control terminal thereof electrically connected to the second control node, a second control terminal thereof electrically connected to a second clock signal line, an input terminal thereof electrically connected to a fourth level signal line, and an output terminal thereof electrically connected to the output terminal of the shift register.

公开(公告)号：US09865201B2

公开(公告)日：2018-01-09

申请号：US14465737

申请日：2014-08-21

Applicant: Shanghai Avic Opto Electronics Co., Ltd. ,  Tianma Micro-Electronics Co., Ltd.

Inventor： Bo Liu ,  Jiongliang Fu ,  Shoufu Jian ,  Zhiqiang Xia ,  Kerui Xi

IPC: G06F3/041 ,  G09G3/36 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1368 ,  H01L27/12 ,  H05K1/02 ,  G02F1/1333

CPC classification number: G09G3/36 ,  G02F1/13338 ,  G02F1/133514 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/134372 ,  G06F3/0412 ,  G06F2203/04101 ,  G06F2203/04103 ,  G09G3/3659 ,  G09G3/3666 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0202 ,  G09G2310/0208 ,  G09G2310/0218 ,  G09G2310/0262 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2320/0613 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H05K1/02

Abstract: A pixel structure is disclosed. The pixel structure includes a substrate, a plurality of scan lines, and a plurality of data lines crossing the scan lines to form pixel unit areas, where the data lines are insulated from the scan lines. The pixel structure also includes a plurality of first electrodes formed in the pixel unit areas, a plurality of second electrodes insulated from the first electrodes and located closer to the substrate than the first electrodes, and a plurality of signal lines located in a same layer as topmost electrodes farthest from the substrate, where the signal lines are arranged to be insulated from the topmost electrodes.

公开(公告)号：US09805640B2

公开(公告)日：2017-10-31

申请号：US15219009

申请日：2016-07-25

Applicant: SHANGHAI AVIC OPTO ELECTRONICS CO., LTD. ,  TIANMA MICRO-ELECTRONICS CO., LTD.

Inventor： Huijun Jin ,  Zhiqiang Xia

IPC: G09G3/20 ,  G09G5/00

CPC classification number: G09G3/2092 ,  G09G3/20 ,  G09G5/003 ,  G09G2300/08 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/0267 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08

Abstract: Embodiments of the invention provide a gate drive apparatus and a display apparatus. With the gate drive apparatus, a clock signal is used in place of a forward scan signal and/or a clock signal is used in place of a backward scan signal and/or a reset signal and a first initial trigger signal (or a second initial trigger signal) are used in place of a low level signal and/or the same signal is used as a first initial trigger signal and a second initial trigger signal to thereby reduce the number of transmission lines for signals driving the gate drive apparatus.