公开(公告)号：US20120168827A1

公开(公告)日：2012-07-05

申请号：US13417706

申请日：2012-03-12

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/786 ,  H01L29/04

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。

公开(公告)号：US20110147852A1

公开(公告)日：2011-06-23

申请号：US12984261

申请日：2011-01-04

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L27/092

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US07545002B2

公开(公告)日：2009-06-09

申请号：US11067836

申请日：2005-02-28

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/0922 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US07391292B2

公开(公告)日：2008-06-24

申请号：US10839424

申请日：2004-05-05

申请人： Shigenobu Maeda ,  Jeong-hwan Yang

发明人： Shigenobu Maeda ,  Jeong-hwan Yang

IPC分类号： H01F5/00

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip inductor includes a main inductor portion configured to provide a main magnetic field of an on-chip inductor. An interconnect inductor portion is electrically coupled to the main inductor portion and is configured to provide an interconnect magnetic field that constructively combines with the main magnetic field.

摘要翻译： 片上电感器包括被配置为提供片上电感器的主磁场的主电感器部分。 互连电感器部分电耦合到主电感器部分并且被配置为提供与主磁场建构性组合的互连磁场。

公开(公告)号：US20080064157A1

公开(公告)日：2008-03-13

申请号：US11981153

申请日：2007-10-31

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

公开(公告)号：US07339213B2

公开(公告)日：2008-03-04

申请号：US11024616

申请日：2004-12-29

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/06

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

公开(公告)号：US20050017836A1

公开(公告)日：2005-01-27

申请号：US10839424

申请日：2004-05-05

申请人： Shigenobu Maeda ,  Jeong-hwan Yang

发明人： Shigenobu Maeda ,  Jeong-hwan Yang

IPC分类号： H01F17/00 ,  H01F5/00 ,  H01L21/02 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip inductor includes a main inductor portion configured to provide a main magnetic field of an on-chip inductor. An interconnect inductor portion is electrically coupled to the main inductor portion and is configured to provide an interconnect magnetic field that constructively combines with the main magnetic field.

摘要翻译： 片上电感器包括被配置为提供片上电感器的主磁场的主电感器部分。 互连电感器部分电耦合到主电感器部分并且被配置为提供与主磁场建构性组合的互连磁场。

公开(公告)号：US07964454B2

公开(公告)日：2011-06-21

申请号：US11981153

申请日：2007-10-31

申请人： Shigenobu Maeda ,  Jeong Hwan Yang

发明人： Shigenobu Maeda ,  Jeong Hwan Yang

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

摘要翻译： 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US20080211022A1

公开(公告)日：2008-09-04

申请号：US12008232

申请日：2008-01-09

申请人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

发明人： Shigenobu Maeda ,  Jeong Hwan Yang ,  Junga Choi

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/7854 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

摘要翻译： 在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。 有源区具有顶表面和侧表面，并且在第一方向上定向。 栅电介质形成在有源区的顶表面和侧表面上。 通道形成在有源区域的顶表面和侧表面中。 栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。 在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。 在SOI层上形成多栅极晶体管。 第一方向和第二方向相同，或者第一方向相对于第二方向成45度。 在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。 在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。

公开(公告)号：US20170077097A1

公开(公告)日：2017-03-16

申请号：US15010327

申请日：2016-01-29

申请人： YAOQI DONG ,  Mun Hyeon Kim ,  Keun Hwi Cho ,  Shigenobu Maeda ,  Han Su Oh

发明人： YAOQI DONG ,  Mun Hyeon Kim ,  Keun Hwi Cho ,  Shigenobu Maeda ,  Han Su Oh

IPC分类号： H01L27/092 ,  H01L29/161 ,  H01L23/535 ,  H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L23/535 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Provided is a semiconductor device having first and second gate electrodes. The semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode crossing the active region and extending in a second direction, and a second gate electrode extending in the second direction on the first gate electrode, wherein the first gate electrode has a first width in the first direction, and wherein the second gate electrode has a second width in the first direction, the second width being less than the first width.

摘要翻译： 提供了具有第一和第二栅电极的半导体器件。 半导体器件包括衬底，在衬底上沿第一方向延伸的有源区，与有源区交叉并沿第二方向延伸的第一栅极，以及在第一栅电极上沿第二方向延伸的第二栅电极， 其中所述第一栅极具有在所述第一方向上的第一宽度，并且其中所述第二栅极具有在所述第一方向上的第二宽度，所述第二宽度小于所述第一宽度。