公开(公告)号：US10827952B2

公开(公告)日：2020-11-10

申请号：US16097552

申请日：2017-04-28

申请人： Shihui Yin ,  Jae-sun Seo ,  Sang Joon Kim ,  Chisung Bae

发明人： Shihui Yin ,  Jae-sun Seo ,  Sang Joon Kim ,  Chisung Bae

IPC分类号： G06K9/00 ,  A61B5/117 ,  G06F21/32 ,  H04L29/06 ,  A61B5/0452 ,  A61B5/00 ,  H04W12/06 ,  A61B5/0456 ,  G06N3/04 ,  G06N3/08

摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining an electrocardiographic (ECG) signal of a user; obtaining a feature vector of the ECG signal of the user with neural network based feature extraction. Comparing the feature vector of the ECG signal with a stored feature vector of a registered user. Authenticating the user in response to determining that a similarity of the ECG feature vector of the ECG signal and the stored ECG feature vector of the registered user exceeds a pre-defined threshold value.

公开(公告)号：US20170300815A1

公开(公告)日：2017-10-19

申请号：US15487117

申请日：2017-04-13

申请人： Jae-sun Seo

发明人： Jae-sun Seo

IPC分类号： G06N3/08 ,  G06N3/04

CPC分类号： G06N3/08 ,  G06N3/063

摘要： An information processing system, which includes a control system and an artificial neural network, is disclosed. The artificial neural network includes a group of neurons and a group of synapses, which includes a first portion and a second portion. The control system selects one of a group of operating modes. The group of neurons processes information. The group of synapses provide connectivity to each of the group of neurons. During a first operating mode of the group of operating modes, the first portion of the group of synapses is enabled and the second portion of the group of synapses is enabled. During a second operating mode of the group of operating modes, the first portion of the group of synapses is enabled and the second portion of the group of synapses is disabled.

公开(公告)号：US07913101B2

公开(公告)日：2011-03-22

申请号：US11824410

申请日：2007-06-29

申请人： Himanshu Kaul ,  Jae-sun Seo ,  Ram K. Krishnamurthy

发明人： Himanshu Kaul ,  Jae-sun Seo ,  Ram K. Krishnamurthy

IPC分类号： G06F1/12

CPC分类号： H03K5/135 ,  H03K2005/00058 ,  H03K2005/00234 ,  H03K2005/00241

摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。

公开(公告)号：US20200349247A1

公开(公告)日：2020-11-05

申请号：US16864902

申请日：2020-05-01

申请人： Jae-sun Seo ,  Shihui Yin ,  Sai Kiran Cherupally

发明人： Jae-sun Seo ,  Shihui Yin ,  Sai Kiran Cherupally

IPC分类号： G06F21/32 ,  H04L9/32 ,  H04L9/08 ,  G06N3/08 ,  A61B5/00

摘要： A smart hardware security engine using biometric features and hardware-specific features is provided. The smart security engine can combine one or more entropy sources, including individually distinguishable biometric features, and hardware-specific features to perform secret key generation for user registration and authentication. Such hybrid signatures may be distinct from person-to-person (e.g., due to the biometric features) and from device-to-device (e.g., due to the hardware-specific features) while varying over time. Thus, embodiments described herein can be used for personal device authentication as well as secret random key generation, significantly reducing the scope of an attack.

公开(公告)号：US20190244100A1

公开(公告)日：2019-08-08

申请号：US16335775

申请日：2017-09-21

申请人： Jae-sun SEO ,  Minkyu KIM ,  ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

发明人： Jae-sun Seo ,  Minkyu Kim

IPC分类号： G06N3/08 ,  G06F7/48

CPC分类号： G06N3/08 ,  G06F7/48 ,  G06N3/0454

摘要： Techniques are described for efficiently reducing the amount of total computation in convolutional neural networks (CNNs) without affecting the output result or classification accuracy. Computation redundancy in CNNs is reduced by exploiting the computing nature of the convolution and subsequent pooling (e.g., sub-sampling) operations. In some implementations, the input features may be divided into a group of precision values and the operation(s) may be cascaded. A maximum may be identified (e.g., by 90% probability) using a small number of bits in the input features, and the full-precision convolution may then be performed on the maximum input. Accordingly, the total number of bits used to perform the convolution is reduced without affecting the output features or the final classification accuracy.

公开(公告)号：US20120259804A1

公开(公告)日：2012-10-11

申请号：US13083414

申请日：2011-04-08

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/04 ,  G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

公开(公告)号：US08242811B2

公开(公告)日：2012-08-14

申请号：US12758189

申请日：2010-04-12

申请人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

发明人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

IPC分类号： H03K3/00

CPC分类号： G06F13/4072 ,  G06F2213/0038 ,  H03K3/3565 ,  Y02D10/14 ,  Y02D10/151

摘要： Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.

摘要翻译： 本发明的一些实施例提供了用于高带宽片上通信的技术和系统。 在操作期间，系统接收将通过芯片中的导线传输的输入电压信号。 然后，该系统从输入电压信号产生一个或多个修改的电压信号。 接下来，系统通过相应的电容器驱动每个电压信号（即，输入电压信号和一个或多个修改的电压信号）。 然后，系统组合来自电容器的输出信号以获得组合电压信号。 接下来，系统通过电线传输组合的电压信号。 所传送的信号然后可以由滞后接收器接收，该滞后接收器通过耦合电容耦合到导线。

公开(公告)号：US20110248750A1

公开(公告)日：2011-10-13

申请号：US12758189

申请日：2010-04-12

申请人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

发明人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

IPC分类号： H03K3/00

CPC分类号： G06F13/4072 ,  G06F2213/0038 ,  H03K3/3565 ,  Y02D10/14 ,  Y02D10/151

摘要： Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.

摘要翻译： 本发明的一些实施例提供了用于高带宽片上通信的技术和系统。 在操作期间，系统接收将通过芯片中的导线传输的输入电压信号。 然后，该系统从输入电压信号产生一个或多个修改的电压信号。 接下来，系统通过相应的电容器驱动每个电压信号（即，输入电压信号和一个或多个修改的电压信号）。 然后，系统组合来自电容器的输出信号以获得组合电压信号。 接下来，系统通过电线传输组合的电压信号。 所传送的信号然后可以由滞后接收器接收，该滞后接收器通过耦合电容耦合到导线。

公开(公告)号：US20230129133A1

公开(公告)日：2023-04-27

申请号：US18047374

申请日：2022-10-18

申请人： Jae-sun Seo ,  Deepak Kadetotad ,  Chaitali Chakrabarti ,  Visar Berisha

发明人： Jae-sun Seo ,  Deepak Kadetotad ,  Chaitali Chakrabarti ,  Visar Berisha

IPC分类号： G06N3/08

摘要： Hierarchical coarse-grain sparsity for deep neural networks is provided. An algorithm-hardware co-optimized memory compression technique is proposed to compress deep neural networks in a hardware-efficient manner, which is referred to herein as hierarchical coarse-grain sparsity (HCGS). HCGS provides a new long short-term memory (LSTM) training technique which enforces hierarchical structured sparsity by randomly dropping static block-wise connections between layers. HCGS maintains the same hierarchical structured sparsity throughout training and inference; this reduces weight storage for both training and inference hardware systems.

公开(公告)号：US11556779B2

公开(公告)日：2023-01-17

申请号：US16335775

申请日：2017-09-21

申请人： ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY ,  Jae-sun Seo ,  Minkyu Kim

发明人： Jae-sun Seo ,  Minkyu Kim

IPC分类号： G06N3/08 ,  G06N3/04 ,  G06F7/48

摘要： Techniques are described for efficiently reducing the amount of total computation in convolutional neural networks (CNNs) without affecting the output result or classification accuracy. Computation redundancy in CNNs is reduced by exploiting the computing nature of the convolution and subsequent pooling (e.g., sub-sampling) operations. In some implementations, the input features may be divided into a group of precision values and the operation(s) may be cascaded. A maximum may be identified (e.g., by 90% probability) using a small number of bits in the input features, and the full-precision convolution may then be performed on the maximum input. Accordingly, the total number of bits used to perform the convolution is reduced without affecting the output features or the final classification accuracy.