公开(公告)号：US06784866B2

公开(公告)日：2004-08-31

申请号：US09824345

申请日：2001-04-02

申请人： Shinya Udo ,  Masatoshi Kokubun

发明人： Shinya Udo ,  Masatoshi Kokubun

IPC分类号： G09G336

CPC分类号： G09G3/3685 ,  G09G3/3607 ,  G09G3/3614 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2330/023

摘要： In a data driver 10A of a dot-inversion driving type, the outputs of voltage buffer amplifiers B1 to B12 are connected to respective data bus lines D1 to D12 of a LCD panel, short-circuiting switches S1, S3, S5, S7, S9 and S11 are connected between ones of every other adjacent data bus lines concerned with the same display color, and interconnecting lines on first and second rows are arranged in a staggered configuration. These short-circuiting switches are formed at one sides of every other data bus lines, and turned on by a control circuit 13 when the outputs of the voltage buffer amplifier are in a high impedance state.

摘要翻译： 在点反转驱动型的数据驱动器10A中，电压缓冲放大器B1〜B12的输出与LCD面板的数据总线D1〜D12连接，短路开关S1，S3，S5，S7，S9 S11相连接在相邻的相邻的数据总线之间，并具有相同的显示颜色，第一行和第二行的互连线以交错的配置排列。 这些短路开关形成在每隔一条数据总线的一侧，当电压缓冲放大器的输出处于高阻抗状态时，由控制电路13导通。

公开(公告)号：US06608612B2

公开(公告)日：2003-08-19

申请号：US09441134

申请日：1999-11-17

申请人： Masatoshi Kokubun ,  Shinya Udo

发明人： Masatoshi Kokubun ,  Shinya Udo

IPC分类号： G09G336

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2310/027 ,  H03M1/76

摘要： A selector circuit comprises four 2-input selectors 50 to 53 each selecting in response to the complementary selection signals D2 and *D2 of MSB and a 4-input selector 24A selecting in response to complementary selection signals D1, *D1, D0 and *D0 of the lower 2 bit. In each of the 2-input selectors 50 to 53, one ends of two switching transistors are commonly connected to each other and the two switching transistors are adjacently arranged in the same row. In the 4-input selector 24A, 4 analogue switch circuits, each of which has two switching transistors arranged in the same row and serially connected, are arranged in parallel to one another and each is arranged in the same row as that of a corresponding 2-input selector. Same selectors are arranged in a row on a substrate and trunk lines for providing two families of gradation potentials V0 to V7 to the circuits are laid above the circuits. Upper/lower trunk line pairs are in the third and second wiring layer, respectively. The distance between adjacent trunk lines in the same wiring layer is 2d in a connecting area and is d in a non-connecting area. A trunk line in the third wiring layer is branched toward adjacent trunk line, and the branched line is connected through an interlayer contact to a line parallel to a trunk line in the second wiring layer.

摘要翻译： 选择器电路包括四个双输入选择器50至53，每个选择器响应于MSB的互补选择信号D2和* D2和响应于互补选择信号D1，* D1，D0和* D0而选择的4输入选择器24A 的低2位。 在每个2-输入选择器50至53中，两个开关晶体管的一端共同连接，并且两个开关晶体管相邻布置在同一行中。 在4输入选择器24A中，4个模拟开关电路中的每一个具有布置在同一行并且串联的两个开关晶体管彼此平行布置，并且每个与相应的2 输入选择器。 相同的选择器在衬底上排列成一行，并且将用于向电路提供两组梯度电位V0至V7的中继线设置在电路之上。 上/下干线对分别在第三和第二布线层中。 在相同布线层中的相邻干线之间的距离在连接区域中为2d，在非连接区域为d。 第三布线层中的干线被分支到相邻的干线，并且分支线通过层间接触连接到与第二布线层中的干线平行的线。

公开(公告)号：US20050270264A1

公开(公告)日：2005-12-08

申请号：US11181774

申请日：2005-07-15

申请人： Masatoshi Kokubun ,  Shinya Udo ,  Chikara Tsuchiya

发明人： Masatoshi Kokubun ,  Shinya Udo ,  Chikara Tsuchiya

IPC分类号： G09G3/20 ,  G09G3/36 ,  H03F1/02 ,  H03F1/34 ,  H03F3/34 ,  H03F3/345 ,  H03F3/45 ,  H03F3/50 ,  H03L5/00

CPC分类号： G09G3/3685 ,  H03F3/45753

摘要： A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.

公开(公告)号：US20050077957A1

公开(公告)日：2005-04-14

申请号：US10811431

申请日：2004-03-29

申请人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

发明人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

IPC分类号： G09G3/36 ,  G09G3/20 ,  H03F3/45 ,  H03F1/02

CPC分类号： H03F3/45753 ,  G09G3/3688

摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

摘要翻译： 提供能够在较短时间内抵消抵消的运算放大器以及能够缩短一个水平周期的线路驱动器和液晶显示装置。 在本发明的运算放大器中，通过将一个水平周期的一个水平周期H1的输出电压VO定义为偏移消除准备中的基准电压的结构，可以缩短反馈控制所需的时间 从而通过反馈控制仅偏移电压VO（2）来改变输出电压VO（2）。 在本发明的线路驱动器中，未用于显示数据D1至D6的输出的运算放大器进行偏移消除操作，并且每隔一个水平周期依次移位。 由于不需要在偏移消除准备期间中包含输出期间，所以可以进一步缩短一个水平周期。

公开(公告)号：US06586990B2

公开(公告)日：2003-07-01

申请号：US10102722

申请日：2002-03-22

申请人： Shinya Udo ,  Masatoshi Kokubun

发明人： Shinya Udo ,  Masatoshi Kokubun

IPC分类号： H03F102

CPC分类号： H03F3/45753

摘要： An operational amplifier, which generates an output voltage at an output terminal that is equal to an input voltage, comprises: a differential circuit, which compares the input voltage and the output voltage; first and second output transistors, which are controlled by the output of the differential circuit to drive the output terminal; and an offset cancel circuit, connected with the differential circuit, for storing an offset amount of this differential circuit, wherein, in the offset cancel period in which the offset amount is stored by the offset cancel circuit, the output terminal is driven by the second output transistor, and in the operational amplifier operation period following the offset cancel period, the output terminal is driven by the first output transistor.

公开(公告)号：US07880537B2

公开(公告)日：2011-02-01

申请号：US12000995

申请日：2007-12-19

申请人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

发明人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

IPC分类号： H03F1/02

CPC分类号： H03F3/45753 ,  G09G3/3688

摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

摘要翻译： 提供能够在较短时间内抵消抵消的运算放大器以及能够缩短一个水平周期的线路驱动器和液晶显示装置。 在本发明的运算放大器中，通过将一个水平周期的一个水平周期H1的输出电压VO定义为偏移消除准备中的基准电压的结构，可以缩短反馈控制所需的时间 从而通过反馈控制仅偏移电压VO（2）来改变输出电压VO（2）。 在本发明的线路驱动器中，未用于显示数据D1至D6的输出的运算放大器进行偏移消除操作，并且每隔一个水平周期依次移位。 由于不需要在偏移消除准备期间中包含输出期间，所以可以进一步缩短一个水平周期。

公开(公告)号：US07460097B2

公开(公告)日：2008-12-02

申请号：US10930856

申请日：2004-09-01

申请人： Seiji Yamagata ,  Masatoshi Kokubun ,  Shinya Udo

发明人： Seiji Yamagata ,  Masatoshi Kokubun ,  Shinya Udo

IPC分类号： G09G3/36 ,  G09G3/38 ,  G09G5/10 ,  G01R31/00

CPC分类号： G09G3/3688 ,  G09G3/006 ,  G09G3/2011 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2310/027 ,  G09G2310/0297 ,  Y10S345/904

摘要： Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

摘要翻译： 作为一组，将保持数字图像数据的数据锁存器的下层数据和正选择器置于正的灰度等级电压线正上方，用于选择正的灰度等级的正模拟灰度电压，并且上位数据锁存器保持数字图像数据和 将用于选择负灰度级的负模拟灰度电压的负灰度级电压线正上方的负选择器作为一组。 两组在垂直方向排列成对准。 水平排列的多组垂直排列的组相对于灰度电压线缩短水平方向的长度。

公开(公告)号：US07358946B2

公开(公告)日：2008-04-15

申请号：US11181774

申请日：2005-07-15

申请人： Masatoshi Kokubun ,  Shinya Udo ,  Chikara Tsuchiya

发明人： Masatoshi Kokubun ,  Shinya Udo ,  Chikara Tsuchiya

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  H03F3/45753

摘要： A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.

摘要翻译： 差分放大电路11包括具有分别连接MOS晶体管M 8和M 9的漏极的第一和第二电流端的电流镜电路，以及具有栅极的一对差分MOS晶体管M 1和M 2，开关SW 1连接。 参考电位Vref被施加到MOS晶体管M 9的栅极。 开关SW 2连接在输出缓冲器电路12的输出VO和MOS晶体管M 1的栅极之间，开关SW 3连接在输出VO和MOS晶体管M8的栅极之间。 在偏移取消准备期间，开关SW 1和SW 3接通，开关SW 2断开。 接下来，开关SW 1至SW 3翻转，从而输出偏移抵消电位VO。

公开(公告)号：US07242427B2

公开(公告)日：2007-07-10

申请号：US10055901

申请日：2002-01-28

申请人： Masatoshi Kokubun ,  Katsuyosi Yamamoto ,  Shinya Udo ,  Jun Funakoshi ,  Chikara Tsuchiya

发明人： Masatoshi Kokubun ,  Katsuyosi Yamamoto ,  Shinya Udo ,  Jun Funakoshi ,  Chikara Tsuchiya

IPC分类号： H04N5/217

CPC分类号： H04N5/378 ,  H04N5/343 ,  H04N5/347

摘要： The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.

摘要翻译： 本发明涉及一种通过CMOS工艺制造的XY地址型固态摄像装置，其目的是提供一种XY地址型固态摄像装置，其中芯片面积不增加，制造成本被抑制， 并且可以执行图像平均处理。 像素区域Pmn以由水平选择线RWm和垂直选择线CLn限定的区域中的矩阵形式排列。 每个像素区Pmn包括光电二极管10，用于将光电二极管10的电荷转换成电压并放大以输出图像数据的源极跟随器放大器14以及用于将图像数据输出到预定的水平选择晶体管16 垂直选择线CLn之一。 放大器/噪声消除电路6具有内置图像平均电路，用于对从多个像素区域Pmn中的至少两个输出的图像数据进行平均处理。

公开(公告)号：US20060226899A1

公开(公告)日：2006-10-12

申请号：US11448669

申请日：2006-06-08

申请人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

发明人： Toshihiko Kasai ,  Shinya Udo ,  Masatoshi Kokubun ,  Yoshihiro Kizaki

IPC分类号： H03F1/02

CPC分类号： H03F3/45753 ,  G09G3/3688

摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.