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公开(公告)号：US06448836B2
公开(公告)日：2002-09-10
申请号：US09731710
申请日：2000-12-08
IPC分类号： H03L500
CPC分类号： H03F3/45753
摘要： An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.
摘要翻译： 用于运算放大器的偏移消除电路包括用于存储由运算放大器部分放大并且包含偏移的电压的电容元件，并且用于基于所存储的电压反馈控制运算放大器部分的电压值，以及切换 用于基于存储在电容元件中的电压的值，在电容元件中的电压的存储和反馈控制之间切换操作的元件。 可以使用电容元件和开关元件来精确地抵消运算放大器部分中的偏移，而不增加运算放大器部分中的晶体管的栅极面积。
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公开(公告)号：US06914631B2
公开(公告)日：2005-07-05
申请号：US10042240
申请日：2002-01-11
CPC分类号： H04N5/363
摘要： The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.
摘要翻译： 本发明涉及一种通过CMOS工艺制造的XY地址型固态摄像装置，其目的是提供一种具有小元件尺寸和宽开口率的XY地址型固态图像拾取装置，并且可以 降低kTC噪声。 在每个像素区域Pmn中形成光电二极管10，复位晶体管12，源极跟随放大器14和水平选择晶体管16。 在像素区域Pmn的外部形成用于降低kTC噪声的kTC噪声降低电路6 VR 1和CDS电路6 CL 1。 差分放大器由每个像素区域Pmn中的kTC降噪电路6 VR 1的第一差分晶体管62和源极跟随放大器14构成。
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公开(公告)号：US20050270264A1
公开(公告)日：2005-12-08
申请号：US11181774
申请日：2005-07-15
申请人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
发明人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
IPC分类号： G09G3/20 , G09G3/36 , H03F1/02 , H03F1/34 , H03F3/34 , H03F3/345 , H03F3/45 , H03F3/50 , H03L5/00
CPC分类号： G09G3/3685 , H03F3/45753
摘要： A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
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4.发明授权Offset cancel circuit of voltage follower equipped with operational amplifier 失效具有运算放大器的电压跟随器的偏移消除电路公开(公告)号：US07358946B2
公开(公告)日：2008-04-15
申请号：US11181774
申请日：2005-07-15
申请人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
发明人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , H03F3/45753
摘要： A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
摘要翻译： 差分放大电路11包括具有分别连接MOS晶体管M 8和M 9的漏极的第一和第二电流端的电流镜电路，以及具有栅极的一对差分MOS晶体管M 1和M 2，开关SW 1连接。 参考电位Vref被施加到MOS晶体管M 9的栅极。 开关SW 2连接在输出缓冲器电路12的输出VO和MOS晶体管M 1的栅极之间，开关SW 3连接在输出VO和MOS晶体管M8的栅极之间。 在偏移取消准备期间，开关SW 1和SW 3接通，开关SW 2断开。 接下来，开关SW 1至SW 3翻转，从而输出偏移抵消电位VO。
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5.发明授权X-Y address type solid-state image pickup device with an image averaging circuit disposed in the noise cancel circuit 有权具有设置在噪声消除电路中的图像平均电路的X-Y地址型固态图像拾取装置公开(公告)号：US07242427B2
公开(公告)日：2007-07-10
申请号：US10055901
申请日：2002-01-28
IPC分类号： H04N5/217
摘要： The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.
摘要翻译： 本发明涉及一种通过CMOS工艺制造的XY地址型固态摄像装置，其目的是提供一种XY地址型固态摄像装置，其中芯片面积不增加，制造成本被抑制， 并且可以执行图像平均处理。 像素区域Pmn以由水平选择线RWm和垂直选择线CLn限定的区域中的矩阵形式排列。 每个像素区Pmn包括光电二极管10，用于将光电二极管10的电荷转换成电压并放大以输出图像数据的源极跟随器放大器14以及用于将图像数据输出到预定的水平选择晶体管16 垂直选择线CLn之一。 放大器/噪声消除电路6具有内置图像平均电路，用于对从多个像素区域Pmn中的至少两个输出的图像数据进行平均处理。
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6.发明授权Offset cancel circuit of voltage follower equipped with operational amplifier 有权具有运算放大器的电压跟随器的偏移消除电路公开(公告)号：US06946905B2
公开(公告)日：2005-09-20
申请号：US10301649
申请日：2002-11-22
申请人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
发明人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
IPC分类号： G09G3/20 , G09G3/36 , H03F1/02 , H03F1/34 , H03F3/34 , H03F3/345 , H03F3/45 , H03F3/50 , H03L5/00
CPC分类号： G09G3/3685 , H03F3/45753
摘要： A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
摘要翻译： 差分放大电路11包括具有分别连接MOS晶体管M 8和M 9的漏极的第一和第二电流端的电流镜电路，以及具有栅极的一对差分MOS晶体管M 1和M 2，开关SW 1连接。 参考电位Vref被施加到MOS晶体管M 9的栅极。 开关SW 2连接在输出缓冲器电路12的输出VO和MOS晶体管M 1的栅极之间，开关SW 3连接在输出VO和MOS晶体管M8的栅极之间。 在偏移取消准备期间，开关SW 1和SW 3接通，开关SW 2断开。 接下来，开关SW 1至SW 3翻转，从而输出偏移抵消电位VO。
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公开(公告)号：US20080252369A1
公开(公告)日：2008-10-16
申请号：US12000995
申请日：2007-12-19
IPC分类号： H03F1/30
CPC分类号： H03F3/45753 , G09G3/3688
摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.
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公开(公告)号：US06864873B2
公开(公告)日：2005-03-08
申请号：US09733075
申请日：2000-12-11
申请人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
发明人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
CPC分类号： G09G3/3688 , G09G3/006 , G09G3/2011 , G09G3/3614 , G09G2300/0426 , G09G2310/027 , G09G2310/0297 , Y10S345/904
摘要： Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
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公开(公告)号：US20050024315A1
公开(公告)日：2005-02-03
申请号：US10930856
申请日：2004-09-01
申请人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
发明人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
CPC分类号： G09G3/3688 , G09G3/006 , G09G3/2011 , G09G3/3614 , G09G2300/0426 , G09G2310/027 , G09G2310/0297 , Y10S345/904
摘要： Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
摘要翻译： 作为一组，将保持数字图像数据的数据锁存器的下层数据和正选择器置于正的灰度等级电压线正上方，用于选择正的灰度等级的正模拟灰度电压，并且上位数据锁存器保持数字图像数据和 将用于选择负灰度级的负模拟灰度电压的负灰度级电压线正上方的负选择器作为一组。 两组在垂直方向排列成对准。 水平排列的多组垂直排列的组相对于灰度电压线缩短水平方向的长度。
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10.发明授权公开(公告)号：US07336124B2
公开(公告)日：2008-02-26
申请号：US11448669
申请日：2006-06-08
IPC分类号： H03F1/02
CPC分类号： H03F3/45753 , G09G3/3688
摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.
摘要翻译： 提供能够在较短时间内抵消抵消的运算放大器以及能够缩短一个水平周期的线路驱动器和液晶显示装置。 在本发明的运算放大器中，通过将一个水平周期的一个水平周期H 1的输出电压VO定义为偏移消除中的基准电压的结构，可以缩短反馈控制所需的时间 准备期间HC 2，从而仅通过反馈控制将偏置电压VO（2）改变输出电压VO（2）。 在本发明的线驱动器中，未用于显示数据D 1至D 6的输出的运算放大器进行偏移消除操作，并且在每一个水平周期上依次移位。 由于不需要在偏移消除准备期间中包含输出期间，所以可以进一步缩短一个水平周期。
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