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公开(公告)号：US07336124B2
公开(公告)日：2008-02-26
申请号：US11448669
申请日：2006-06-08
IPC分类号： H03F1/02
CPC分类号： H03F3/45753 , G09G3/3688
摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.
摘要翻译： 提供能够在较短时间内抵消抵消的运算放大器以及能够缩短一个水平周期的线路驱动器和液晶显示装置。 在本发明的运算放大器中，通过将一个水平周期的一个水平周期H 1的输出电压VO定义为偏移消除中的基准电压的结构，可以缩短反馈控制所需的时间 准备期间HC 2，从而仅通过反馈控制将偏置电压VO（2）改变输出电压VO（2）。 在本发明的线驱动器中，未用于显示数据D 1至D 6的输出的运算放大器进行偏移消除操作，并且在每一个水平周期上依次移位。 由于不需要在偏移消除准备期间中包含输出期间，所以可以进一步缩短一个水平周期。
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公开(公告)号：US07081792B2
公开(公告)日：2006-07-25
申请号：US10811431
申请日：2004-03-29
IPC分类号： H03F1/02
CPC分类号： H03F3/45753 , G09G3/3688
摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.
摘要翻译： 提供能够在较短时间内抵消抵消的运算放大器以及能够缩短一个水平周期的线路驱动器和液晶显示装置。 在本发明的运算放大器中，通过将一个水平周期的一个水平周期H 1的输出电压VO定义为偏移消除中的基准电压的结构，可以缩短反馈控制所需的时间 准备期间HC 2，从而仅通过反馈控制将偏置电压VO（2）改变输出电压VO（2）。 在本发明的线驱动器中，未用于显示数据D 1至D 6的输出的运算放大器进行偏移消除操作，并且在每一个水平周期上依次移位。 由于不需要在偏移消除准备期间中包含输出期间，所以可以进一步缩短一个水平周期。
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公开(公告)号：US06914631B2
公开(公告)日：2005-07-05
申请号：US10042240
申请日：2002-01-11
CPC分类号： H04N5/363
摘要： The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.
摘要翻译： 本发明涉及一种通过CMOS工艺制造的XY地址型固态摄像装置，其目的是提供一种具有小元件尺寸和宽开口率的XY地址型固态图像拾取装置，并且可以 降低kTC噪声。 在每个像素区域Pmn中形成光电二极管10，复位晶体管12，源极跟随放大器14和水平选择晶体管16。 在像素区域Pmn的外部形成用于降低kTC噪声的kTC噪声降低电路6 VR 1和CDS电路6 CL 1。 差分放大器由每个像素区域Pmn中的kTC降噪电路6 VR 1的第一差分晶体管62和源极跟随放大器14构成。
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公开(公告)号：US06784866B2
公开(公告)日：2004-08-31
申请号：US09824345
申请日：2001-04-02
申请人： Shinya Udo , Masatoshi Kokubun
发明人： Shinya Udo , Masatoshi Kokubun
IPC分类号： G09G336
CPC分类号： G09G3/3685 , G09G3/3607 , G09G3/3614 , G09G2310/0248 , G09G2310/0297 , G09G2330/023
摘要： In a data driver 10A of a dot-inversion driving type, the outputs of voltage buffer amplifiers B1 to B12 are connected to respective data bus lines D1 to D12 of a LCD panel, short-circuiting switches S1, S3, S5, S7, S9 and S11 are connected between ones of every other adjacent data bus lines concerned with the same display color, and interconnecting lines on first and second rows are arranged in a staggered configuration. These short-circuiting switches are formed at one sides of every other data bus lines, and turned on by a control circuit 13 when the outputs of the voltage buffer amplifier are in a high impedance state.
摘要翻译： 在点反转驱动型的数据驱动器10A中，电压缓冲放大器B1〜B12的输出与LCD面板的数据总线D1〜D12连接，短路开关S1，S3，S5，S7，S9 S11相连接在相邻的相邻的数据总线之间，并具有相同的显示颜色，第一行和第二行的互连线以交错的配置排列。 这些短路开关形成在每隔一条数据总线的一侧，当电压缓冲放大器的输出处于高阻抗状态时，由控制电路13导通。
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5.发明授权Selector and multilayer interconnection with reduced occupied area on substrate 有权选择器和多层互连，减少衬底占用面积公开(公告)号：US06608612B2
公开(公告)日：2003-08-19
申请号：US09441134
申请日：1999-11-17
申请人： Masatoshi Kokubun , Shinya Udo
发明人： Masatoshi Kokubun , Shinya Udo
IPC分类号： G09G336
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/027 , H03M1/76
摘要： A selector circuit comprises four 2-input selectors 50 to 53 each selecting in response to the complementary selection signals D2 and *D2 of MSB and a 4-input selector 24A selecting in response to complementary selection signals D1, *D1, D0 and *D0 of the lower 2 bit. In each of the 2-input selectors 50 to 53, one ends of two switching transistors are commonly connected to each other and the two switching transistors are adjacently arranged in the same row. In the 4-input selector 24A, 4 analogue switch circuits, each of which has two switching transistors arranged in the same row and serially connected, are arranged in parallel to one another and each is arranged in the same row as that of a corresponding 2-input selector. Same selectors are arranged in a row on a substrate and trunk lines for providing two families of gradation potentials V0 to V7 to the circuits are laid above the circuits. Upper/lower trunk line pairs are in the third and second wiring layer, respectively. The distance between adjacent trunk lines in the same wiring layer is 2d in a connecting area and is d in a non-connecting area. A trunk line in the third wiring layer is branched toward adjacent trunk line, and the branched line is connected through an interlayer contact to a line parallel to a trunk line in the second wiring layer.
摘要翻译： 选择器电路包括四个双输入选择器50至53，每个选择器响应于MSB的互补选择信号D2和* D2和响应于互补选择信号D1，* D1，D0和* D0而选择的4输入选择器24A 的低2位。 在每个2-输入选择器50至53中，两个开关晶体管的一端共同连接，并且两个开关晶体管相邻布置在同一行中。 在4输入选择器24A中，4个模拟开关电路中的每一个具有布置在同一行并且串联的两个开关晶体管彼此平行布置，并且每个与相应的2 输入选择器。 相同的选择器在衬底上排列成一行，并且将用于向电路提供两组梯度电位V0至V7的中继线设置在电路之上。 上/下干线对分别在第三和第二布线层中。 在相同布线层中的相邻干线之间的距离在连接区域中为2d，在非连接区域为d。 第三布线层中的干线被分支到相邻的干线，并且分支线通过层间接触连接到与第二布线层中的干线平行的线。
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公开(公告)号：US20080252369A1
公开(公告)日：2008-10-16
申请号：US12000995
申请日：2007-12-19
IPC分类号： H03F1/30
CPC分类号： H03F3/45753 , G09G3/3688
摘要： An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.
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公开(公告)号：US06864873B2
公开(公告)日：2005-03-08
申请号：US09733075
申请日：2000-12-11
申请人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
发明人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
CPC分类号： G09G3/3688 , G09G3/006 , G09G3/2011 , G09G3/3614 , G09G2300/0426 , G09G2310/027 , G09G2310/0297 , Y10S345/904
摘要： Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
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公开(公告)号：US20050024315A1
公开(公告)日：2005-02-03
申请号：US10930856
申请日：2004-09-01
申请人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
发明人： Seiji Yamagata , Masatoshi Kokubun , Shinya Udo
CPC分类号： G09G3/3688 , G09G3/006 , G09G3/2011 , G09G3/3614 , G09G2300/0426 , G09G2310/027 , G09G2310/0297 , Y10S345/904
摘要： Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
摘要翻译： 作为一组，将保持数字图像数据的数据锁存器的下层数据和正选择器置于正的灰度等级电压线正上方，用于选择正的灰度等级的正模拟灰度电压，并且上位数据锁存器保持数字图像数据和 将用于选择负灰度级的负模拟灰度电压的负灰度级电压线正上方的负选择器作为一组。 两组在垂直方向排列成对准。 水平排列的多组垂直排列的组相对于灰度电压线缩短水平方向的长度。
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公开(公告)号：US06448836B2
公开(公告)日：2002-09-10
申请号：US09731710
申请日：2000-12-08
IPC分类号： H03L500
CPC分类号： H03F3/45753
摘要： An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.
摘要翻译： 用于运算放大器的偏移消除电路包括用于存储由运算放大器部分放大并且包含偏移的电压的电容元件，并且用于基于所存储的电压反馈控制运算放大器部分的电压值，以及切换 用于基于存储在电容元件中的电压的值，在电容元件中的电压的存储和反馈控制之间切换操作的元件。 可以使用电容元件和开关元件来精确地抵消运算放大器部分中的偏移，而不增加运算放大器部分中的晶体管的栅极面积。
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公开(公告)号：US20060256052A1
公开(公告)日：2006-11-16
申请号：US11487339
申请日：2006-07-17
IPC分类号： G09G3/36
CPC分类号： G09G3/006
摘要： A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.
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