摘要:
An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.
摘要:
The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.
摘要:
A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
摘要:
A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
摘要:
The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.
摘要:
A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
摘要:
A CMOS image sensor that reduces kTC noise in a wide band. A pixel circuit corresponding to one pixel includes a photoelectric conversion element for carrying out the photoelectric conversion of incident light, a reset transistor for resetting a cathode of the photoelectric conversion element to initial voltage, an amplifying transistor for converting electric charges accumulated in the photoelectric conversion element to voltage, and a row selection transistor for selecting signals output from pixel areas arranged in a row direction. A voltage control circuit controls the potential of a gate of the reset transistor during a period when the photoelectric conversion element is reset to change ON-state resistance of the reset transistor. By doing so, a cutoff frequency for a low-pass filter formed in the pixel circuit by ON-state resistance of the reset transistor and parasitic capacitance produced at the cathode on the photoelectric conversion element will be controlled.
摘要:
The CMOS sensor circuit comprises a photodiode, a reset transistor resetting the photodiode to an initial voltage, and a voltage control circuit controlling a gate potential of the reset transistor to a potential other than power source potentials. The voltage control circuit consists of an inverter circuit driving a gate of the reset transistor. The inverter circuit includes a P-channel MOS transistor, an N-channel MOS transistor, and a transistor inserted between a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor so as to control a blooming.
摘要:
A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.
摘要:
A DC/DC converter enabling an increase in frequency. The DC/DC converter includes a main transistor, a synchronization transistor, a control circuit, which controls the main transistor and the synchronization transistor, and a capacitor, which is charged to generate gate voltage for the main transistor. The control circuit includes a charging time setting circuit for setting the activation time of the main transistor and the synchronization transistor.
摘要翻译:DC / DC转换器,能够提高频率。 DC / DC转换器包括主晶体管,同步晶体管,控制主晶体管和同步晶体管的控制电路以及被充电以产生主晶体管的栅极电压的电容器。 控制电路包括用于设定主晶体管和同步晶体管的激活时间的充电时间设定电路。