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72 条记录 (耗时 0.025 秒)

    Data programming circuits and memory programming methods
    11.
    发明授权
    Data programming circuits and memory programming methods 有权
    数据编程电路和存储器编程方法

    公开(公告)号：US08218361B2

    公开(公告)日：2012-07-10

    申请号：US13215491

    申请日：2011-08-23

    申请人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

    发明人： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

    摘要： A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

    摘要翻译： 提供了一种用于将写入数据存储到存储单元中的数据编程电路。 数据编程电路包括控制电路和电流产生电路。 控制电路根据写入数据生成控制信号。 电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。 写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

    Device controlling phase change storage element and method thereof
    12.
    发明授权
    Device controlling phase change storage element and method thereof 有权
    装置控制相变存储元件及其方法

    公开(公告)号：US07796455B2

    公开(公告)日：2010-09-14

    申请号：US12142724

    申请日：2008-06-19

    申请人： Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

    发明人： Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

    IPC分类号： G11C7/02

    CPC分类号： G11C5/14 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078

    摘要： Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.

    摘要翻译： 控制相变存储元件的装置和增加相变存储元件的可靠性的方法。 本发明引入了第一操作模式和第二操作模式。 参考相变存储元件在第一操作模式中强制写入电流以达到理想的导通时段。 在第二操作模式中，本发明基于参考相变存储元件的电阻产生适当的导通周期，并将写入电流强制到受控相变存储元件中以达到适当的导通周期。

    VERIFICATION CIRCUITS AND METHODS FOR PHASE CHANGE MEMORY ARRAY
    14.
    发明申请
    VERIFICATION CIRCUITS AND METHODS FOR PHASE CHANGE MEMORY ARRAY 有权
    验证电路和相位变化记忆阵列的方法

    公开(公告)号：US20100165720A1

    公开(公告)日：2010-07-01

    申请号：US12485720

    申请日：2009-06-16

    申请人： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

    发明人： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

    IPC分类号： G11C11/00 ,  G11C7/06

    CPC分类号： G11C13/0064 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

    摘要： A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state

    摘要翻译： 提供了一种用于相变存储器阵列的验证电路。 感测单元根据使能信号感测来自相变存储器阵列的存储单元的感测电压。 比较器根据感测电压和参考电压产生比较信号，以指示存储器单元是否处于复位状态。 控制单元根据使能信号产生控制信号。 操作单元根据控制信号生成第一信号，以指示比较器是否有效。 调整单元向单元提供写入电流，并根据控制信号增加写入电流，直到比较信号指示存储单元处于复位状态

    Phase change memory
    16.
    发明授权
    Phase change memory 有权
    相变记忆

    公开(公告)号：US08199561B2

    公开(公告)日：2012-06-12

    申请号：US12563971

    申请日：2009-09-21

    申请人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

    发明人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0092

    摘要： A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

    摘要翻译： 具有可逐渐增加或逐渐减小的工作电流的相变存储器。 相变存储器具有相变存储元件，晶体管和控制电路。 晶体管可操作以调节流过相变存储元件的工作电流。 晶体管具有耦合到电压源的第一端子，耦合到相变存储元件的第二端子以及从控制电路接收控制信号的控制端子。 控制电路专门设计用于将晶体管限制在线性区域。

    Verification circuits and methods for phase change memory array
    17.
    发明授权
    Verification circuits and methods for phase change memory array 有权
    相变存储器阵列的验证电路和方法

    公开(公告)号：US07974122B2

    公开(公告)日：2011-07-05

    申请号：US12485720

    申请日：2009-06-16

    申请人： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

    发明人： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0064 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

    摘要： A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.

    摘要翻译： 提供了一种用于相变存储器阵列的验证电路。 感测单元根据使能信号感测来自相变存储器阵列的存储单元的感测电压。 比较器根据感测电压和参考电压产生比较信号，以指示存储器单元是否处于复位状态。 控制单元根据使能信号产生控制信号。 操作单元根据控制信号生成第一信号，以指示比较器是否有效。 调整单元向单元提供写入电流，并且根据控制信号增加写入电流，直到比较信号指示存储单元处于复位状态。

    Phase Change Memory
    18.
    发明申请
    Phase Change Memory 有权
    相变记忆

    公开(公告)号：US20100165722A1

    公开(公告)日：2010-07-01

    申请号：US12561245

    申请日：2009-09-16

    申请人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

    发明人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004

    摘要： A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.

    摘要翻译： 相变存储元件通过逐渐增加/减小的工作电流而结晶化的相变存储器（PCM）。 PCM包括开关电路，相变存储元件，位选择开关，脉冲发生模块和计数模块。 开关电路包括多个开关，选择性地提供到电流源的输出端的分支路径。 位选择开关控制相变存储元件与电流源的输出端之间的导通。 脉冲发生模块输出在高电平和低电压电平之间振荡的脉冲信号。 当使能时，计数模块对脉冲信号的振荡进行计数，并通过一组数字数据输出计数结果。 该组数字数据耦合到开关电路以控制其中的开关。

    Phase change memory
    20.
    发明授权
    Phase change memory 有权
    相变记忆

    公开(公告)号：US08605493B2

    公开(公告)日：2013-12-10

    申请号：US13477884

    申请日：2012-05-22

    申请人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

    发明人： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0092

    摘要： A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

    摘要翻译： 具有可逐渐增加或逐渐减小的工作电流的相变存储器。 相变存储器具有相变存储元件，晶体管和控制电路。 晶体管可操作以调节流过相变存储元件的工作电流。 晶体管具有耦合到电压源的第一端子，耦合到相变存储元件的第二端子以及从控制电路接收控制信号的控制端子。 控制电路专门设计用于将晶体管限制在线性区域。