公开(公告)号：US20240184697A1

公开(公告)日：2024-06-06

申请号：US18524982

申请日：2023-11-30

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Richard Van

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/121

Abstract: Systems and methods are disclosed for data storage in a non-inclusive cache. For example, an integrated circuit may include a cache that includes a databank with multiple entries configured to store respective cache lines; and an array of cache tags, wherein each cache tag includes a data pointer that points to an entry in the databank. For example, methods may include allocating the entry in the databank to the cache including the array of cache tags from amongst multiple caches in the integrated circuit by writing the data pointer to the cache tag in the array of cache tags.

公开(公告)号：US11922101B2

公开(公告)日：2024-03-05

申请号：US18123422

申请日：2023-03-20

Applicant: SiFive, Inc.

Inventor： Yunsup Lee ,  Richard Xia ,  Derek Pappas ,  Mark Nugent ,  Henry Cook ,  Wesley Waylon Terpstra ,  Pin Hung Chen

IPC: G06F30/20 ,  G06F30/30

CPC classification number: G06F30/20 ,  G06F30/30

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

公开(公告)号：US20230195980A1

公开(公告)日：2023-06-22

申请号：US17992976

申请日：2022-11-23

Applicant: SiFive, Inc.

Inventor： Ryan Macdonald ,  Erik Arthur Daine ,  Wesley Waylon Terpstra ,  Yunsup Lee

IPC: G06F30/31 ,  G06F30/327

CPC classification number: G06F30/31 ,  G06F30/327

Abstract: Systems and methods are disclosed for integrated circuit design using integrated circuit shells. For example, a system may generate an integrated circuit core design expressed in a hardware description language. The integrated circuit core design may express circuitry that describes one or more functions to be included in an application specific integrated circuit (ASIC). The one or more functions may have connection points providing first inputs and outputs to the one or more functions. The system may query an integrated circuit shell expressed in a hardware description language. The integrated circuit shell may express circuitry that describes a limited set of pads to be implemented in the ASIC. The limited set of pads may provide second inputs and outputs to the integrated circuit. The query may determine availability of pads of the limited set of pads to connect to the connection points of the one or more functions.

公开(公告)号：US20230029660A1

公开(公告)日：2023-02-02

申请号：US17961137

申请日：2022-10-06

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

公开(公告)号：US20220261522A1

公开(公告)日：2022-08-18

申请号：US17734332

申请日：2022-05-02

Applicant: SiFive, Inc.

Inventor： Henry Cook ,  Ernest L. Edgar ,  Ryan Macdonald ,  Wesley Waylon Terpstra

IPC: G06F30/327 ,  G06F30/333

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US20200042664A1

公开(公告)日：2020-02-06

申请号：US16528911

申请日：2019-08-01

Applicant: SiFive, Inc.

Inventor： Yunsup Lee ,  Richard Xia ,  Derek Pappas ,  Mark Nugent ,  Henry Cook ,  Wesley Waylon Terpstra ,  Pin Hung Chen

IPC: G06F17/50

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

公开(公告)号：US20240184707A1

公开(公告)日：2024-06-06

申请号：US18341244

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/0891

CPC classification number: G06F12/0891

Abstract: An agent may be configured to invoke a first eviction operation that is interruptible by probe operations when receiving a first type of eviction message and invoke a second eviction operation in which probe operations are interruptible by the second eviction operation when receiving a second type of eviction message. In some implementations, the agent may maintain a data storage that is inclusive of at least one of unique or dirty cache blocks in a cache maintained by an agent that transmits the second type of eviction message. In some implementations, the agent may prevent a cache block from transitioning from a modified state to an exclusive state when the agent invokes the second eviction operation to evict the cache block. In some implementations, the agent may convert from the second eviction operation to the first eviction operation when receiving the second type of eviction message.

公开(公告)号：US20240184703A1

公开(公告)日：2024-06-06

申请号：US18341217

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Eric Andrew Gouldey ,  Michael Klinglesmith ,  Henry Cook

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/0815

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0815

Abstract: A method and apparatus for a speculative request indicator is described. A method includes providing, for a cache hierarchy, a messaging protocol used for transfer operations among agents in the cache hierarchy, the messaging protocol indicating acceptable cache coherency states for a cache block indicated in a request message and providing, in the messaging protocol for selection by an agent, a speculative request indicator when sending the request message, wherein the speculative request indicator differentiates between a demand request and a speculative request with respect to the cache block.

公开(公告)号：US20240184701A1

公开(公告)日：2024-06-06

申请号：US18182772

申请日：2023-03-13

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Waylon Terpstra ,  Michael Kinglesmith

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0897

CPC classification number: G06F12/0862 ,  G06F9/30018 ,  G06F12/0897

Abstract: Prefetch circuitry may be configured to transmit a message to cancel a prefetch of one or more cache blocks of a group. The message may correspond to a prefetch message by indicating an address for the group and a bit field for the one or more cache blocks of the group to cancel. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.

公开(公告)号：US11610036B2

公开(公告)日：2023-03-21

申请号：US17361238

申请日：2021-06-28

Applicant: SiFive, Inc.

Inventor： Yunsup Lee ,  Richard Xia ,  Derek Pappas ,  Mark Nugent ,  Henry Cook ,  Wesley Waylon Terpstra ,  Pin Hung Chen

IPC: G06F30/20 ,  G06F30/30

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.