公开(公告)号：US20070183209A1

公开(公告)日：2007-08-09

申请号：US11683292

申请日：2007-03-07

申请人： Jim Ni ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： Jim Ni ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G11C11/34

CPC分类号： H05K5/0269 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087 ,  H05K5/026

摘要： A case-grounded flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips and a controller chip. The PCBA is encased inside an upper case and a lower case, with a Serial AT-Attachment (SATA) connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Dual-axis case-grounding pins draw any electro-static-discharges (ESD) current off the upper case along a primary axis and onto a PCBA ground through a secondary axis washer that is screwed into the PCBA. The primary axis body of the dual-axis case-grounding pins fits around a PCBA notch while the secondary axis passes through a metalized alignment hole for grounding. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the dual-axis case-grounding pins.

摘要翻译： 外壳接地闪存驱动器具有带闪存芯片的印刷电路板组件（PCBA）和控制器芯片。 PCBA被封装在上壳体和下壳体内，并具有穿过并在壳体之间打开的串行AT附件（SATA）连接器。 这些情况可以通过卡扣，超声波压力机，螺纹紧固件或热粘合粘合剂方法与PCBA组装。 双轴外壳接地引脚通过螺纹连接到PCBA中的次轴垫圈将初始轴上的任何静电放电（ESD）电流从主轴上吸入PCBA接地。 双轴壳体 - 接地销的主轴体装配在PCBA槽口周围，而副轴线穿过金属化的对准孔进行接地。 当SATA连接器插入主机时，主机接地将吸收由双轴外壳接地引脚收集的ESD电流。

公开(公告)号：US20080086631A1

公开(公告)日：2008-04-10

申请号：US11864652

申请日：2007-09-28

申请人： David Chow ,  Charles Lee ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

发明人： David Chow ,  Charles Lee ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

IPC分类号： G06F15/177 ,  G06F12/02

CPC分类号： G06F8/654

摘要： An electronic data flash card is accessible by a host system, and includes a flash memory controller and at least one flash memory device coupled to the flash controller. The boot code and control code for the flash memory system (flash card) are stored in the flash memory device during a programming procedure. The flash controller transfers the boot code and control code to a volatile main memory (e.g., random access memory or RAM) at start up or reset making a RAM-based memory system. Boot code and control code are selectively overwritten during a code updating operation. A single flash controller thus supports multiple brands and types of flash memory to eliminate stocking issues.

摘要翻译： 电子数据闪存卡可由主机系统访问，并且包括闪存控制器和耦合到闪存控制器的至少一个闪存设备。 闪存系统（闪存卡）的启动代码和控制代码在编程过程中存储在闪存设备中。 闪存控制器在启动或复位时将引导代码和控制代码传送到易失性主存储器（例如，随机存取存储器或RAM），从而形成基于RAM的存储器系统。 引导代码和控制代码在代码更新操作期间被有选择地覆盖。 因此，单个闪存控制器支持多种品牌和类型的闪存，以消除存货问题。

公开(公告)号：US20080082736A1

公开(公告)日：2008-04-03

申请号：US11864684

申请日：2007-09-28

申请人： David Chow ,  Charles Lee ,  Abraham Ma ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

发明人： David Chow ,  Charles Lee ,  Abraham Ma ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7203 ,  G06F2212/7211

摘要： An electronic data flash card accessible by a host computer, includes a flash memory controller connected to a flash memory device, and an input-output interface circuit activated to establish a communication with the host. In an embodiment, the flash card uses a USB interface circuit for communication with the host. A flash memory controller includes an arbitrator for mapping logical addresses with physical block addresses, and for performing block management operations including: storing reassigned data to available blocks, relocating valid data in obsolete blocks to said available blocks and reassigning logical block addresses to physical block addresses of said available blocks, finding bad blocks of the flash memory device and replacing with reserve blocks, erasing obsolete blocks for recycling after relocating valid data to available blocks, and erase count wear leveling of blocks, etc. Furthermore, each flash memory device includes an internal buffer for accelerating the block management operations.

摘要翻译： 由主机可访问的电子数据闪存卡包括连接到闪速存储器件的闪存控制器和被激活以建立与主机的通信的输入 - 输出接口电路。 在一个实施例中，闪存卡使用USB接口电路与主机进行通信。 闪速存储器控制器包括用于将逻辑地址与物理块地址对准的仲裁器，并且用于执行块管理操作，包括：将重新分配的数据存储到可用块，将过时块中的有效数据重定位到所述可用块并将逻辑块地址重新分配给物理块地址 的所述可用块，找到闪存设备的坏块并用备用块替换，在将有效数据重新定位到可用块之后擦除用于再循环的废弃块，以及擦除块的计数损耗均衡等。此外，每个闪存设备包括 内部缓冲区，用于加快块管理操作。

公开(公告)号：US20080065796A1

公开(公告)日：2008-03-13

申请号：US11926636

申请日：2007-10-29

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F13/42

CPC分类号： G06F13/28 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An extended Universal-Serial Bus (EUSB) bridge to a host computer can have Peripheral Components Interconnect Express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.

摘要翻译： 到主机的扩展通用串行总线（EUSB）桥可以在桥的一侧具有外围组件互连Express（PCIE）协议层，在桥的另一侧可以具有高级桥接转换器 模块连接上层。 可以通过将桥与I / O控制器集成来消除PCIE物理，数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥，而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。 然后，EUSB数据有效载荷被传递到EUSB事务层，EUSB数据链路层和EUSB物理层，其在EUSB总线的两个差分对上驱动和感测物理电信号。

公开(公告)号：US20080052452A1

公开(公告)日：2008-02-28

申请号：US11929859

申请日：2007-10-30

申请人： David Chow ,  Frank Yu ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： David Chow ,  Frank Yu ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

公开(公告)号：US20070268754A1

公开(公告)日：2007-11-22

申请号：US11674645

申请日：2007-02-13

申请人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  Ming-Shiang Shen

发明人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G11C16/04 ,  G06F12/00

CPC分类号： H01R13/629 ,  G06F12/0246 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7209 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.

摘要翻译： 闪存块的滑动窗口用于减少闪存中过时数据占用的浪费空间。 滑动窗口向下滑过几个闪光块。 检查最旧的块是否有效的数据页面，有效的页面被复制到滑动窗口的末尾，以便第一个块只有过时的页面。 然后可以擦除第一个块并最终重新使用。 RAM使用表包含滑动窗口中每个块中页面的有效位。 当数据写入页面时，页面的有效位从擦除的未写入状态更改为有效状态。 之后，当新的主机数据替换该数据时，旧页面的有效位被设置为陈旧状态。 RAM陈旧标记表可以跟踪页面中已经有过时的页面。

公开(公告)号：US20070201274A1

公开(公告)日：2007-08-30

申请号：US11737336

申请日：2007-04-19

申请人： Frank Yu ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： Frank Yu ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634 ,  G11C2211/5641

摘要： A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

摘要翻译： 闪存具有多级单元（MLC），每个单元可以存储多个位。 当发生错误时，单元块可以降级到较少的位/单元，或用于存储关键数据（如引导代码）。 来自单个MLC的位在多个页面之间进行分区，以使用错误校正码（ECC）来提高错误的可校正性。 响应于校准寄存器，由参考电压发生器产生较高的参考电压，校准寄存器可编程为改变上参考电压。 从较高参考电压产生一系列减小的参考值，并将其与位线电压进行比较。 比较结果由翻译逻辑翻译，生成读取数据和编程过程中和编程不足的信号。 降级的单元格使用相同的真值表，但生成较少的读取数据位。 通过使用相同的子状态来读取降级和全密度MLC单元，噪声余量被不对称地改善。

公开(公告)号：US20080098164A1

公开(公告)日：2008-04-24

申请号：US11876251

申请日：2007-10-22

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F2212/2022 ,  G06F2212/2515

摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.

摘要翻译： 闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。 引导完成后，SRAM缓冲区还可以作为闪存数据缓存。 缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。 外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。 引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。 闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。 帧，分组和编码时钟处理也由串行接口执行。

公开(公告)号：US20080071963A1

公开(公告)日：2008-03-20

申请号：US11979103

申请日：2007-10-31

申请人： David Chow ,  Sidney Young ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： David Chow ,  Sidney Young ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/20 ,  G06F12/02

CPC分类号： G06F13/409 ,  G06F2213/0026 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

摘要： An ExpressCard having USB connection has a card case having two opposite first and second end portions and two opposite lateral portions. A card connector is formed at the first end portion of the card case and having a USB interface. Flash chips are implemented in the card case. A USB flash controller implemented in the card case and connected between the USB interface and the flash chips in order to provide a data access to the flash chips through the USB interface. A USB socket, in form factors of Mini-USB or Extended Mini-connector-type, is implemented in the card case and connected to the USB flash controller in order to provide a data access to the one or more flash chips therethrough. An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an ExpressCard that is busy performing a memory or other operation, thereby saving power.

摘要翻译： 具有USB连接的ExpressCard具有具有两个相对的第一和第二端部和两个相对的横向部分的卡盒。 卡连接器形成在卡盒的第一端部并且具有USB接口。 闪存芯片在卡盒中实现。 USB闪存控制器实现在卡盒中并连接在USB接口和闪存芯片之间，以通过USB接口提供对闪存芯片的数据访问。 一个USB插座，以Mini-USB或扩展迷你连接器类型的形式被实现在卡盒中并连接到USB闪存控制器，以便提供对一个或多个闪存芯片的数据访问。 扩展的通用串行总线（EUSB）主机进入挂起模式，而不是轮询正忙于执行内存或其他操作的ExpressCard，从而节省电量。

公开(公告)号：US20080065794A1

公开(公告)日：2008-03-13

申请号：US11928124

申请日：2007-10-30

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.

摘要翻译： 扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。 减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。 源是内存组的内存表。 内存表有几个内存段的条目。 每个存储表条目具有指向存储器段的指针和段的字节计数。 一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。 读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。