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公开(公告)号：US10720948B2
公开(公告)日：2020-07-21
申请号：US16410055
申请日：2019-05-13
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Ping Xiong
Abstract: A method for operating a communications system includes transmitting a preamble sequence including a plurality of tones. Each tone of the plurality of tones has a first characteristic and a second characteristic. The first characteristic of each of the tones of the plurality of tones has a predetermined relative relationship to the first characteristic of each of the other tones of the plurality of tones and the second characteristic of each of the tones of the plurality of tones has a predetermined relative relationship to the second characteristic of each of the other tones of the plurality of tones. The first and second characteristics may include relative power and relative phase.
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公开(公告)号：US10312955B1
公开(公告)日：2019-06-04
申请号：US15859894
申请日：2018-01-02
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Ping Xiong
Abstract: A method compensates for a frequency error in a communications system. The method includes detecting a received preamble sequence in a received signal. The received preamble sequence is detected based on a plurality of power estimates corresponding to a plurality of frequency bins of a received frequency domain signal and a plurality of relative phase errors corresponding to the plurality of frequency bins of the received frequency domain signal. The method includes determining the frequency error using the received preamble sequence. The method includes adjusting the receiver based on the frequency error.
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公开(公告)号：US10172105B2
公开(公告)日：2019-01-01
申请号：US15164363
申请日：2016-05-25
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Ping Xiong , Wentao Li
Abstract: An apparatus includes a radio frequency (RF) receiver having a multi-bit observation interval. The RF receiver includes a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal. The RF receiver further includes a timing correlator and frequency offset estimator coupled to receive data derived from a frequency signal derived from the phase signal. The RF receiver in addition includes a Viterbi decoder coupled to provide decoded data derived from the frequency signal.
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公开(公告)号：US10008981B2
公开(公告)日：2018-06-26
申请号：US15096612
申请日：2016-04-12
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost , Hendricus de Ruijter
IPC: H03B5/08 , H03B5/12 , H03L1/00 , H03B5/36 , H03L1/02 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/22 , H03L7/23 , H03L7/183 , H03L7/197
CPC classification number: H03B5/1234 , H03B5/12 , H03B5/1265 , H03B5/36 , H03L1/00 , H03L1/026 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/183 , H03L7/1976 , H03L7/22 , H03L7/23
Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.
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公开(公告)号：US20180159658A1
公开(公告)日：2018-06-07
申请号：US15370693
申请日：2016-12-06
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Ping Xiong , Wentao Li
CPC classification number: H04L1/0054 , H04L1/0047 , H04L7/042 , H04L27/22
Abstract: An apparatus includes a radio frequency (RF) receiver, which includes a differentiator to differentiate a phase signal to generate a differentiated signal. The RF receiver further includes a correlator coupled to receive and correlate the differentiated signal, and a memory to receive and store the differentiated signal. Samples of the differentiated signal are provided to the correlator and to the memory synchronously.
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Patent Agency Ranking
公开(公告)号：US09736709B2
公开(公告)日：2017-08-15
申请号：US14500382
申请日：2014-09-29
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter , Wentao Li
IPC: H04L12/26 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04W24/08 , H04L27/10 , H04L27/12 , H04L27/148
CPC classification number: H04W24/08 , H04L27/106 , H04L27/12 , H04L27/148
Abstract: A receiver includes an analog receiver and a digital processor. The analog receiver has an input for receiving a radio frequency (RF) signal, and an output for providing a digital intermediate frequency signal. The digital processor has an input for receiving the digital intermediate frequency signal, and an output for providing digital symbols. The digital processor measures peak-to-peak frequency deviation of the digital intermediate frequency signal, and performs a digital signal processing function on the digital intermediate frequency signal to provide the digital symbols based on the peak-to-peak frequency deviation so measured.
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公开(公告)号：US09510289B1
公开(公告)日：2016-11-29
申请号：US14934058
申请日：2015-11-05
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter
CPC classification number: H04W52/0235 , H03L7/148 , Y02D70/144 , Y02D70/26
Abstract: A wireless transceiver includes receiver front-end circuitry for processing an ingoing radio frequency (RF) signal to produce an in-going digital signal to a processor connected to receive the in-going digital signal. The processor includes sync word determination logic configured to identify a received sync word or other event or connection point and to subsequently generate an event determination signal. A low power oscillator produces low frequency pulses to a first counter. A crystal oscillator that produces higher frequency pulses to a second counter is used for the last portion of the desired sleep time for greater resolution. Thus, a calibration controller receives pulse counts from at least one of the first and second counters and determines a period between a common event of subsequent beacon signals or connection events and determines wake up times based on the received pulse counts from at least one of the first and second counters.
Abstract translation: 无线收发器包括接收机前端电路，用于处理入射射频（RF）信号以产生正在进行的数字信号到连接的处理器以接收正在进行的数字信号。 处理器包括被配置为识别所接收的同步字或其他事件或连接点并且随后生成事件确定信号的同步字确定逻辑。 低功率振荡器产生低频脉冲到第一个计数器。 在第二计数器产生较高频率脉冲的晶体振荡器用于所需睡眠时间的最后部分，以获得更高的分辨率。 因此，校准控制器从第一和第二计数器中的至少一个计数器接收脉冲计数，并且确定后续信标信号或连接事件的公共事件之间的周期，并且基于从至少一个的接收到的脉冲计数确定唤醒时间 第一和第二柜台。
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公开(公告)号：US20160226443A1
公开(公告)日：2016-08-04
申请号：US15096612
申请日：2016-04-12
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost , Hendricus de Ruijter
CPC classification number: H03B5/1234 , H03B5/12 , H03B5/1265 , H03B5/36 , H03L1/00 , H03L1/026 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/183 , H03L7/1976 , H03L7/22 , H03L7/23
Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.
Abstract translation: 集成时钟发生器包括可调谐LC振荡器，可调频率合成器和处理器。 可调LC振荡器具有用于接收振荡器控制信号的输入端和用于提供振荡器时钟信号的输出端。 可调频率合成器具有耦合到可调谐LC振荡器的输出的时钟输入，用于接收合成器控制信号的控制输入和用于提供时钟输出信号的输出。 处理器具有用于接收数据输入信号的输入端，用于提供振荡器控制信号的第一输出端和用于提供合成器控制信号的第二输出端。 处理器提供振荡器控制信号和合成器控制信号，使得可调谐频率合成器以由数据输入信号指示的频率生成输出时钟信号，并且响应于动态条件进一步提供合成器控制信号。
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公开(公告)号：US20150381772A1
公开(公告)日：2015-12-31
申请号：US14317902
申请日：2014-06-27
Applicant: Silicon Laboratories Inc.
Inventor： Hendricus de Ruijter
CPC classification number: H04L1/0083 , H04L1/1607
Abstract: An apparatus includes a transceiver having a MAC controller and a PHY controller. The MAC controller is configured to selectively omit at least a portion of a field of a media access control (MAC) frame. The PHY controller is configured to insert the MAC frame into a physical protocol data unit and to selectively configure a portion of the physical protocol data unit to indicate omission of at least the portion of the field from the MAC frame.
Abstract translation: 一种装置包括具有MAC控制器和PHY控制器的收发器。 MAC控制器被配置为选择性地省略媒体访问控制（MAC）帧的字段的至少一部分。 PHY控制器被配置为将MAC帧插入到物理协议数据单元中，并且有选择地配置物理协议数据单元的一部分以指示从MAC帧至少部分字段的省略。
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20.发明公开公开(公告)号：US20230412205A1
公开(公告)日：2023-12-21
申请号：US18241172
申请日：2023-08-31
Applicant: Silicon Laboratories Inc.
Inventor： Antonio Torrini , Hendricus de Ruijter , Yan Zhou , David Trager
Abstract: An apparatus includes a radio-frequency (RF) receiver for receiving an RF signal using a plurality of antennas. The RF receiver includes a demodulator to provide a switch signal to cause the RF receiver to use an antenna in the plurality of antennas. The RF receiver further includes a carrier frequency offset (CFO) correction circuit that estimates and removes a carrier frequency offset.
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