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公开(公告)号：USRE48275E1
公开(公告)日：2020-10-20
申请号：US15217364
申请日：2016-07-22
发明人： Aaron J. Caffee , Brian G. Drost
摘要： A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.
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公开(公告)号：US10523211B2
公开(公告)日：2019-12-31
申请号：US15239552
申请日：2016-08-17
发明人： Brian G. Drost
摘要： A divider includes ⅔ divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A ⅔ divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.
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公开(公告)号：US09634678B1
公开(公告)日：2017-04-25
申请号：US15052985
申请日：2016-02-25
发明人： Aaron J. Caffee , Brian G. Drost , Vaibhav Karkare
CPC分类号： H03L7/187 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/183 , H03L2207/50
摘要： A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.
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公开(公告)号：US20160373120A1
公开(公告)日：2016-12-22
申请号：US14745545
申请日：2015-06-22
发明人： Aaron J. Caffee , Brian G. Drost
CPC分类号： H03L7/091 , G06F1/022 , H03K5/135 , H03L7/081 , H03L7/0814 , H03L7/0891 , H03L7/093 , H03L7/183 , H03L7/1976
摘要： A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.
摘要翻译： 用于校准数字 - 时间转换器的技术包括一种包括数字 - 时间转换器的装置，其被配置为基于数字码，输入信号和增益校准信号来产生输出信号。 输出信号具有基于数字码从输入信号的相应边缘线性延迟的边缘。 数字代码在评估代码和校准代码之间摇摆。 该装置包括被配置为提供输入信号的延迟版本的参考信号发生器。 参考信号发生器的延迟与数字 - 时间转换器的延迟相匹配。 该装置包括校准电路，其被配置为基于输出信号和输入信号的延迟版本来生成增益校准信号。 校准代码可以在第一校准延迟代码和第二校准延迟代码之间交替。
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公开(公告)号：US09362936B1
公开(公告)日：2016-06-07
申请号：US14745534
申请日：2015-06-22
发明人： Aaron J. Caffee , Brian G. Drost
摘要： A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.
摘要翻译： 数字 - 时间转换器包括第一节点，被配置为接收参考信号的第二节点和配置成将被动阻抗耦合到第一节点的数模转换信号转换器。 根据数字码选择被动阻抗。 数字到时间转换器还包括第一开关，其被配置为响应于输入信号选择性地将第一节点耦合到第二参考信号，以及配置成基于第一节点上的第一信号生成输出信号的比较器， 参考信号在第二个节点上。 数字到时间转换器可以包括被配置为响应于第一控制信号而选择性地将第一节点耦合到第三参考信号的第二开关。
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公开(公告)号：US20200007136A1
公开(公告)日：2020-01-02
申请号：US16022188
申请日：2018-06-28
摘要： A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals.
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公开(公告)号：US20200006314A1
公开(公告)日：2020-01-02
申请号：US16019746
申请日：2018-06-27
发明人： Aaron J. Caffee , Brian G. Drost
IPC分类号： H01L27/01 , H03M1/80 , H01L23/522 , H01L49/02
摘要： An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.
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8.发明授权公开(公告)号：US09804573B1
公开(公告)日：2017-10-31
申请号：US15394454
申请日：2016-12-29
发明人： Brian G. Drost , Ankur Guha Roy
CPC分类号： G04F10/005 , H03M1/0692 , H03M1/14 , H03M1/16 , H03M1/188 , H03M1/60
摘要： A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.
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公开(公告)号：US09698807B1
公开(公告)日：2017-07-04
申请号：US15199257
申请日：2016-06-30
CPC分类号： H03M1/66 , H03L7/081 , H03L7/183 , H03M1/1033 , H03M1/1057 , H03M1/68 , H03M1/82
摘要： A technique for on-chip time measurement includes dynamically scaling a range of a time-based digital-to-analog converter to enhance resolution of the time measurement. An apparatus includes a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock signal and a first digital code. The apparatus includes a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock signal and a second digital code. The first reference clock signal has a first frequency and the second reference clock signal has a second frequency that is harmonically related to the first frequency. The apparatus includes a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.
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公开(公告)号：US09509278B2
公开(公告)日：2016-11-29
申请号：US13828066
申请日：2013-03-14
CPC分类号： H03H9/2457 , H03B5/30 , H03H9/02259 , H03H9/02275 , H03H9/2431 , H03H2009/02291 , H03H2009/02346 , H03H2009/02496
摘要： An apparatus includes a microelectromechanical system (MEMS) device. The MEMS device includes a resonator suspended from a substrate, an anchor disposed at a center of the resonator, a plurality of suspended beams radiating between the anchor and the resonator, a plurality of first electrodes disposed about the anchor, and a plurality of second electrodes disposed about the anchor. The plurality of first electrodes and the resonator form a first electrostatic transducer. The plurality of second electrodes and the resonator form a second electrostatic transducer. The first electrostatic transducer and the second electrostatic transducer are configured to sustain rotational vibrations of the resonator at a predetermined frequency about an axis through the center of the resonator and orthogonal to a plane of the substrate in response to a signal on the first electrode.
摘要翻译： 一种装置包括微机电系统（MEMS）装置。 MEMS器件包括从衬底悬挂的谐振器，设置在谐振器中心的锚，在锚和谐振器之间辐射的多个悬臂，围绕锚定器设置的多个第一电极和多个第二电极 围绕锚点布置。 多个第一电极和谐振器形成第一静电换能器。 多个第二电极和谐振器形成第二静电换能器。 第一静电换能器和第二静电换能器被配置为响应于第一电极上的信号，以围绕谐振器的中心的轴线以预定的频率维持谐振器的旋转振动并且与基板的平面正交。
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