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    Providing low power charge pump for integrated circuit
    11.
    发明授权
    Providing low power charge pump for integrated circuit 有权

    公开(公告)号：US11543843B2

    公开(公告)日：2023-01-03

    申请号：US17230266

    申请日：2021-04-14

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Tak Ying Wong ,  Ricky Setiawan

    IPC: G05F1/575 ,  H02M3/07

    Abstract: In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.

    Digital oversampling clock and data recovery circuit
    12.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US10461920B2

    公开(公告)日：2019-10-29

    申请号：US15884650

    申请日：2018-01-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

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