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    Digital Oversampling Clock And Data Recovery Circuit
    1.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 审中-公开

    公开(公告)号：US20190379524A1

    公开(公告)日：2019-12-12

    申请号：US16546691

    申请日：2019-08-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital oversampling clock and data recovery circuit
    3.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US10826677B2

    公开(公告)日：2020-11-03

    申请号：US16546691

    申请日：2019-08-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital Oversampling Clock And Data Recovery Circuit
    4.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 审中-公开

    公开(公告)号：US20180152280A1

    公开(公告)日：2018-05-31

    申请号：US15884650

    申请日：2018-01-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital Oversampling Clock And Data Recovery Circuit
    5.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 有权

    公开(公告)号：US20170366330A1

    公开(公告)日：2017-12-21

    申请号：US15182951

    申请日：2016-06-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    POWER-SAVING POWER ARCHITECTURE FOR INTEGRATED CIRCUITS SUCH AS MICROCONTROLLERS
    6.
    发明申请
    POWER-SAVING POWER ARCHITECTURE FOR INTEGRATED CIRCUITS SUCH AS MICROCONTROLLERS 有权

    公开(公告)号：US20210311540A1

    公开(公告)日：2021-10-07

    申请号：US16841138

    申请日：2020-04-06

    Applicant: Silicon Laboratories Inc.

    Inventor： Rex Tak Ying Wong ,  Ricky Setiawan ,  Hua Beng Chan ,  Yushan Jiang ,  Pio Balmelli

    IPC: G06F1/3237 ,  H02M1/00 ,  G06F1/3234 ,  G06F1/28 ,  G06F1/3296

    Abstract: An integrated circuit includes a first plurality of circuits receiving a first internal power supply voltage, a first regulator receiving an external power supply voltage and supplying the first internal power supply voltage at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode, a second regulator receiving the external power supply voltage for supplying the first internal power supply voltage at a second rated power less than said first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode, and a controller controlling a transition of the integrated circuit between the active mode and the low power mode. The controller activates all of the first plurality of circuits in the active mode, but only a subset of them while keeping remaining ones inactive in the low power mode.

    Providing low power charge pump for integrated circuit
    7.
    发明授权
    Providing low power charge pump for integrated circuit 有权

    公开(公告)号：US11029716B1

    公开(公告)日：2021-06-08

    申请号：US16793154

    申请日：2020-02-18

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Tak Ying Wong ,  Ricky Setiawan

    IPC: G05F1/575 ,  H02M3/07

    Abstract: In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.

    Digital oversampling clock and data recovery circuit
    8.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US09923710B2

    公开(公告)日：2018-03-20

    申请号：US15182951

    申请日：2016-06-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Voltage regulator having minimal fluctuation in multiple operating modes
    10.
    发明授权
    Voltage regulator having minimal fluctuation in multiple operating modes 有权

    公开(公告)号：US12189408B2

    公开(公告)日：2025-01-07

    申请号：US17847404

    申请日：2022-06-23

    Applicant: Silicon Laboratories Inc.

    Inventor： Ricky Setiawan ,  Hua Beng Chan ,  Rex Tak Ying Wong

    IPC: G05F1/575 ,  G06F1/30

    Abstract: In an embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a first loop circuit coupled to the amplifier to receive the comparison signal and output a first feedback voltage for the amplifier to use as the feedback voltage in a first mode of operation; and a second loop circuit coupled to the amplifier. The second loop circuit may be configured to receive the comparison signal and output a second feedback voltage for the amplifier to use as the feedback voltage in a second mode of operation. The second feedback voltage may be greater than the first feedback voltage, and the second loop circuit may output a regulated voltage based on the comparison signal.

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