公开(公告)号：US20190065055A1

公开(公告)日：2019-02-28

申请号：US15863449

申请日：2018-01-05

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F3/06

Abstract: A data storage device includes a flash memory and a controller. The flash memory is utilized to store at least one data. The controller is coupled to the flash memory to receive at least one read command transmitted from a host, and reads the data stored by the flash memory according to the read command. The controller determines whether or not the length of the read command is greater than a first predetermined value. If the length is greater than the first predetermined value, the controller arranges the read command on a sequential queue. If the length is not greater than the first predetermined value, the controller arranges the read command on a random queue. The controller executes the read command of the random queue at high priority.

公开(公告)号：US09292432B2

公开(公告)日：2016-03-22

申请号：US14452767

申请日：2014-08-06

Applicant: Silicon Motion, Inc.

Inventor： Po-Chia Chu ,  Yu-Chih Lin

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: A garbage collection method for a flash memory is provided. The flash memory includes a spare block pool and a data block pool, wherein the spare block pool includes spare blocks and the data block pool includes data blocks. The method includes the steps of: receiving target data from a host and writing the target data to a current data block of the data blocks; sorting an erase count of each data block when performing a wear-leveling process to write the target data; sorting a valid page number of each first block when it is determined that at least two first blocks in the data blocks have the smallest erase count; and selecting a second block having a smallest valid page number from the first blocks and writing valid pages of the second block to one of the spare blocks to perform a data cleaning process.

Abstract translation: 提供了一种用于闪速存储器的垃圾回收方法。 闪速存储器包括备用块池和数据块池，其中备用块池包括备用块，并且数据块池包括数据块。 该方法包括以下步骤：从主机接收目标数据并将目标数据写入数据块的当前数据块; 当执行磨损均衡处理以写入目标数据时对每个数据块的擦除计数进行排序; 当确定数据块中的至少两个第一块具有最小擦除次数时，排序每个第一块的有效页码; 以及从所述第一块中选择具有最小有效页码的第二块，并将所述第二块的有效页写入所述备用块中的一个以执行数据清理处理。

公开(公告)号：US11994985B2

公开(公告)日：2024-05-28

申请号：US17959320

申请日：2022-10-04

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

公开(公告)号：US20240111670A1

公开(公告)日：2024-04-04

申请号：US17959320

申请日：2022-10-04

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

公开(公告)号：US20210349655A1

公开(公告)日：2021-11-11

申请号：US17082032

申请日：2020-10-28

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F3/06

Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).

公开(公告)号：US10990292B2

公开(公告)日：2021-04-27

申请号：US16413615

申请日：2019-05-16

Applicant: Silicon Motion Inc.

Inventor： Guan-Yao Huang ,  Yu-Chih Lin ,  Chang-Wei Shen

IPC: G06F3/06

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, the flash memory module includes a plurality of flash memory chips, the flash memory controller includes a buffer memory and a microcontroller, and the buffer memory is arranged to store an in-system programming (ISP) code. When the flash memory controller enters a power saving mode, the microcontroller disables a portion of the buffer memory to make at least one portion of the ISP code disappear; and when the flash memory controller enters a normal mode from the power saving mode, the microcontroller reads said at least one portion of the ISP code from N flash memory chips within the plurality of flash memory chips, wherein N is a positive integer greater than one.

公开(公告)号：US10528289B2

公开(公告)日：2020-01-07

申请号：US15863449

申请日：2018-01-05

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F3/06

Abstract: A data storage device includes a flash memory and a controller. The flash memory is utilized to store at least one data. The controller is coupled to the flash memory to receive at least one read command transmitted from a host, and reads the data stored by the flash memory according to the read command. The controller determines whether or not the length of the read command is greater than a first predetermined value. If the length is greater than the first predetermined value, the controller arranges the read command on a sequential queue. If the length is not greater than the first predetermined value, the controller arranges the read command on a random queue. The controller executes the read command of the random queue at high priority.

公开(公告)号：US10140024B2

公开(公告)日：2018-11-27

申请号：US15265563

申请日：2016-09-14

Applicant: Silicon Motion, Inc.

Inventor： Yu-Chih Lin

IPC: G06F3/06 ,  G06F13/16

Abstract: The present invention provides a data storage device including a flash memory, a random access memory, and a controller. The controller selects a first read command where the required mapping table has already been loaded on the random access memory from a plurality of read commands. Before a first read task prepared by the first read command is executed, the controller selects a second read command from the remaining read commands, selectively reads a first data sector of the first read command and the mapping table of the second read command at the same time, or reads the first data sector and a second data sector of the second read command at the same time.

公开(公告)号：US09875032B2

公开(公告)日：2018-01-23

申请号：US15618232

申请日：2017-06-09

Applicant: Silicon Motion, Inc.

Inventor： Chang-Kai Cheng ,  Yu-Chih Lin

IPC: G11C7/00 ,  G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00

Abstract: The present invention provides a data storage device including a flash memory, a controller and a delay circuit. The controller receives a read command from a host, reads a first data sector from the flash memory according to the read command, and produces a setting signal according to the maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit receives the setting signal from the controller, divides the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmits at least one of the first sub-data sectors to the host at a predetermined time interval for extending the busy time of the controller.

公开(公告)号：US09218891B2

公开(公告)日：2015-12-22

申请号：US14091908

申请日：2013-11-27

Applicant: Silicon Motion, Inc.

Inventor： Chia-Chien Wu ,  Yu-Chih Lin ,  Yen-Hung Lin

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/10

Abstract: A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least one replay-protected memory block of the FLASH memory. The controller programs a success flag and a write count into a system block of the FLASH memory after the controller programs two pages into the at least one replay-protected memory block of the FLASH memory. The controller may perform a power restoration process based on the success flag of the system block or/and based on the amount of programmed pages of the at least one replay-protected memory block.

Abstract translation: 一种使用具有重放保护块的闪存的数据存储设备。 FLASH存储器的存储空间被分成块，每个块进一步分为页。 在数据存储设备中提供控制器以耦合到闪速存储器。 控制器管理闪存的至少一个重放保护的存储器块。 在控制器将两个页面编程到FLASH存储器的至少一个重放保护的存储器块之后，控制器将成功标志和写入计数器编程到闪存存储器的系统块中。 控制器可以基于系统块的成功标志或/或基于至少一个重放保护的存储器块的编程页面的量来执行功率恢复处理。