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公开(公告)号：US08626807B2
公开(公告)日：2014-01-07
申请号：US12350680
申请日：2009-01-08
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.
摘要翻译： 一种用于将有符号固定点数转换为浮点数的方法，该浮点数包括读取与要转换的有符号固定点数相对应的输入数，确定输入数是否小于零，根据输入 数量小于零或大于或等于零，通过将输入数字与符号位进行异或运算来计算第一中间结果，计算第一中间结果的前导零，基于符号位填充第一中间结果， 通过将填充的第一中间结果向左移动前导零来计算第二中间结果，计算指数部分和分数部分，基于符号位有条件地增加分数部分，校正指数部分和分数部分，如果 递增分数部分溢出，返回浮点数。
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公开(公告)号：US08578196B2
公开(公告)日：2013-11-05
申请号：US13552327
申请日：2012-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种在处理数学运算时降低功耗的方法和系统。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US08452824B2
公开(公告)日：2013-05-28
申请号：US11872846
申请日：2007-10-16
申请人： Tobias Gemmeke , Jochen Preiss
发明人： Tobias Gemmeke , Jochen Preiss
IPC分类号： G06F15/00
CPC分类号： H03K19/20 , G06F7/00 , G06F9/30029
摘要： A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.
摘要翻译： 描述了对两个输入信号（va，vb）应用任何布尔运算的二进制逻辑单元，其中要施加到输入信号（va，vb）上的任何布尔运算由明确定义的控制信号（ct10 ，ctl1，ctl2，ctl3），其中输入信号（va，vb）用于选择控制信号（ctl0，ctl1，ctl2，ctl3）作为代表a的结果的二进制逻辑单元的输出信号（vo） 特定的布尔运算应用于两个输入信号（va，vb）。 此外，描述了操作这种二进制逻辑单元的方法。
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公开(公告)号：US08291003B2
公开(公告)日：2012-10-16
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译： 在二进制浮点处理器中，通过用结果精度（Emin）的最小指数值偏置指数，将各种类型的操作数中的每一个的指数重新编码为内部格式，即指数的重新编码值为 指数的代表值减去Emin。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。 然后以这种新格式执行指数计算。 对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。 指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。
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公开(公告)号：US08255726B2
公开(公告)日：2012-08-28
申请号：US12176191
申请日：2008-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method, system and computer program product for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种用于在处理数学运算时降低功耗的方法，系统和计算机程序产品。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US20100058266A1
公开(公告)日：2010-03-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译： 用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。
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公开(公告)号：US08407275B2
公开(公告)日：2013-03-26
申请号：US12255968
申请日：2008-10-22
IPC分类号： G06F7/02
CPC分类号： G06F9/30021 , G06F9/30025
摘要： A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
摘要翻译： 浮点处理器单元通过比较整数格式的两个操作数来执行具有相同或不同精度的两个操作数的浮点比较指令，这显着地加快了浮点比较指令的执行。 浮点处理器现在对于几乎大多数操作数情况（例如，所有情况的99％），至少执行两倍快或更快（例如，现有技术中的两个时钟周期而不是五个时钟周期）的浮点比较指令。 只有罕见的角落情况需要在其中一个操作数上进行额外的操作，因此需要额外的执行周期，因为整数比较操作将不适用于这些角色。 这是由于一个操作数是非正规化表示中的单精度子正规数（即，具有两个表示），另一个操作数处于SP子正常范围，使得整数比较操作将失败。
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18.发明授权Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result 有权具有全部和全零检测的移位器，其使用部分移位向量的一部分和平移的移位量以产生移位结果公开(公告)号：US08332453B2
公开(公告)日：2012-12-11
申请号：US12331702
申请日：2008-12-10
IPC分类号： G06F7/00
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译： 一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端， 移位器。 检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作， 并行地移动到由最终变速级执行的换档操作以产生转换结果。
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19.发明授权Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip 有权具有多个可扫描存储元件的半导体芯片和用于扫描半导体芯片上的存储元件的方法公开(公告)号：US07996738B2
公开(公告)日：2011-08-09
申请号：US12042944
申请日：2008-03-05
申请人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
发明人： Tobias Gemmeke , Christoph Jaeschke , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Jochen Preiss
IPC分类号： G01R31/28
CPC分类号： G01R31/318575
摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.
摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。
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20.发明授权Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit 失效设计结构降低时钟门控同步电路和时钟门控同步电路内的功耗公开(公告)号：US07735038B2
公开(公告)日：2010-06-08
申请号：US11850745
申请日：2007-09-06
申请人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
发明人： Tobias Gemmeke , Jens Leenstra , Jochen Preiss
CPC分类号： H03K19/0016
摘要： A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.
摘要翻译： 一种用于降低时钟门控同步电路内的功耗的设计结构，所述同步电路包括至少两个连续级，其中每个级如果被激活，则逐周期地将数据信号周期传播到后级，所述两个连续级包括至少一个控制寄存器 ，数据寄存器和本地时钟缓冲器（LCB），其中每个级如果被激活，则将周期内存储的数据信号周期传播到后级的数据寄存器。
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