公开(公告)号：US08363487B2

公开(公告)日：2013-01-29

申请号：US12784164

申请日：2010-05-20

申请人： Sebastian Ehrenreich ,  Tilman Gloekler ,  Willm Hinrichs ,  Jens Kuenzer

发明人： Sebastian Ehrenreich ,  Tilman Gloekler ,  Willm Hinrichs ,  Jens Kuenzer

IPC分类号： G11C16/04

CPC分类号： G11C29/24 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/1202

摘要： An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.

摘要翻译： 改进的方法监视存储器电路，特别是集成电路中使用的那些电路。 该方法提供：在至少一个监视器单元中写入随机数据，其被实现为具有人为劣化的稳定性的常规存储器单元，以便在与常规存储器单元中的故障相比时引发早期失败; 从所述至少一个监视器单元读取所述随机数据; 将读取操作的输出数据与期望值进行比较以检测值不匹配; 并且如果检测到值不匹配，则将值不匹配报告给错误结构。

公开(公告)号：US07996738B2

公开(公告)日：2011-08-09

申请号：US12042944

申请日：2008-03-05

申请人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

IPC分类号： G01R31/28

CPC分类号： G01R31/318575

摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。

公开(公告)号：US20070172010A1

公开(公告)日：2007-07-26

申请号：US11340449

申请日：2006-01-26

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

IPC分类号： H04L7/00

CPC分类号： G06F1/14 ,  G04F10/04 ,  H03L7/06

摘要： The illustrative embodiments provide a system, apparatus and method for providing accurate time-based counters for scaling operating frequencies of microprocessors. The system, apparatus and method make use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.

摘要翻译： 说明性实施例提供了一种用于提供用于缩放微处理器的操作频率的精确的基于时间的计数器的系统，装置和方法。 系统，装置和方法利用基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL，并用于馈送外部和内部时基逻辑以及 时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。

公开(公告)号：US06989696B2

公开(公告)日：2006-01-24

申请号：US10707066

申请日：2003-11-19

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cédric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler ,  Gerard M. Salem ,  Peter A. Sandon ,  Dana J. Thygesen ,  Ulrich Weiss

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cédric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler ,  Gerard M. Salem ,  Peter A. Sandon ,  Dana J. Thygesen ,  Ulrich Weiss

IPC分类号： H03L7/00

CPC分类号： H03L7/06

摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

摘要翻译： 能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率 信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。 同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。 相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器 基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

公开(公告)号：US20050104637A1

公开(公告)日：2005-05-19

申请号：US10707066

申请日：2003-11-19

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mathew Ringler ,  Gerard Salem ,  Peter Sandon ,  Dana Thygesen ,  Ulrich Weiss

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mathew Ringler ,  Gerard Salem ,  Peter Sandon ,  Dana Thygesen ,  Ulrich Weiss

IPC分类号： H03L7/06

CPC分类号： H03L7/06

摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

摘要翻译： 能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率 信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。 同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。 相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器 基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

公开(公告)号：US20100309734A1

公开(公告)日：2010-12-09

申请号：US12784164

申请日：2010-05-20

申请人： Sebastian Ehrenreich ,  Tilman Gloekler ,  Willm Hinrichs ,  Jens Kuenzer

发明人： Sebastian Ehrenreich ,  Tilman Gloekler ,  Willm Hinrichs ,  Jens Kuenzer

IPC分类号： G11C7/06

CPC分类号： G11C29/24 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/1202

摘要： An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.

摘要翻译： 改进的方法监视存储器电路，特别是集成电路中使用的那些电路。 该方法提供：在至少一个监视器单元中写入随机数据，其被实现为具有人为劣化的稳定性的常规存储器单元，以便在与常规存储器单元中的故障相比时引发早期失败; 从所述至少一个监视器单元读取所述随机数据; 将读取操作的输出数据与期望值进行比较以检测值不匹配; 并且如果检测到不匹配值，则将值不匹配报告给错误结构。

公开(公告)号：US07646838B2

公开(公告)日：2010-01-12

申请号：US12130229

申请日：2008-05-30

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

IPC分类号： H04L7/00

CPC分类号： G06F1/14 ,  G04F10/04 ,  H03L7/06

摘要： The illustrative embodiments provide accurate time-based counters for scaling operating frequencies of microprocessors. A time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.

摘要翻译： 说明性实施例提供用于缩放微处理器的操作频率的精确的基于时间的计数器。 一种基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL，并用于馈送外部和内部时基逻辑以及时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。

公开(公告)号：US20080226008A1

公开(公告)日：2008-09-18

申请号：US12130229

申请日：2008-05-30

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

IPC分类号： H04L7/00

CPC分类号： G06F1/14 ,  G04F10/04 ,  H03L7/06

摘要： The illustrative embodiments provide accurate time-based counters for scaling operating frequencies of microprocessors. A time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.

摘要翻译： 说明性实施例提供用于缩放微处理器的操作频率的精确的基于时间的计数器。 一种基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL，并用于馈送外部和内部时基逻辑以及时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。

公开(公告)号：US07602874B2

公开(公告)日：2009-10-13

申请号：US11340449

申请日：2006-01-26

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Martin Recktenwald ,  Andreas Schmid

IPC分类号： H04L7/00

CPC分类号： G06F1/14 ,  G04F10/04 ,  H03L7/06

摘要： A mechanism provides accurate time-based counters for scaling operating frequencies of microprocessors. The mechanism makes use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.

摘要翻译： 一种机制提供了精确的基于时间的计数器来缩放微处理器的工作频率。 该机制利用基于时间的计数器电路配置，其中从微处理器的时钟产生电路的PLL导出固定频率时钟，并且用于馈送外部和内部时基逻辑以及时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。

公开(公告)号：US20080276140A1

公开(公告)日：2008-11-06

申请号：US12042944

申请日：2008-03-05

申请人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318575

摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。