公开(公告)号：US07996738B2

公开(公告)日：2011-08-09

申请号：US12042944

申请日：2008-03-05

申请人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

IPC分类号： G01R31/28

CPC分类号： G01R31/318575

摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。

公开(公告)号：US20080276140A1

公开(公告)日：2008-11-06

申请号：US12042944

申请日：2008-03-05

申请人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Christoph Jaeschke ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Jochen Preiss

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318575

摘要： A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

摘要翻译： 分为功率域的半导体芯片，至少一个功率域被单独激活或去激活，并且可扫描存储元件的至少一部分互连到一个或多个扫描链。 至少一个扫描链被连续地分成扫描链部分，并且扫描链部分被布置在一个功率域内。 对于至少一个扫描链部分，提供旁路线以通过扫描数据，并且提供至少一个选择单元用于根据相应功率域的激活或去激活状态在旁路线和对应的扫描链部分之间进行选择 。

公开(公告)号：US07735038B2

公开(公告)日：2010-06-08

申请号：US11850745

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： H03K19/0016

摘要： A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.

摘要翻译： 一种用于降低时钟门控同步电路内的功耗的设计结构，所述同步电路包括至少两个连续级，其中每个级如果被激活，则逐周期地将数据信号周期传播到后级，所述两个连续级包括至少一个控制寄存器 ，数据寄存器和本地时钟缓冲器（LCB），其中每个级如果被激活，则将周期内存储的数据信号周期传播到后级的数据寄存器。

公开(公告)号：US20080162897A1

公开(公告)日：2008-07-03

申请号：US11872846

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jochen Preiss

IPC分类号： G06F9/305

CPC分类号： H03K19/20 ,  G06F7/00 ,  G06F9/30029

摘要： A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.

摘要翻译： 描述了用于对两个输入信号（v SUB，a，B）进行任何布尔运算的二进制逻辑单元，其中应用于输入信号的任何布尔运算（v 由定义良好的控制信号（ct10，ct11，ct12，ct13）的特定组合定义，其中输入信号（v 用于选择作为输出信号的控制信号（ct1 0，ct1，ctl2，ct13）作为输出信号（v < / SUB>）表示施加在两个输入信号（v SUB a，v B b）上的特定布尔运算的结果的二进制逻辑单元。 此外，描述了操作这种二进制逻辑单元的方法。

公开(公告)号：US08370409B2

公开(公告)日：2013-02-05

申请号：US12028889

申请日：2008-02-11

申请人： Tobias Gemmeke ,  Nicolas Maeding ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Nicolas Maeding ,  Jochen Preiss

IPC分类号： G06F7/00

CPC分类号： G06F7/727 ,  G06F7/499

摘要： A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.

摘要翻译： 描述了一种操作数宽度减小的方法，其中处理位宽N为N的两个N位输入操作数（A，B），并减少位宽M的M位输出操作数（A'，B'） 以一种方式产生，包括在所述两个M位输出操作数（A'，B'）上执行的对M位进行饱和后的M位加法器功能的后处理提供等于M的M位结果 两个N位输入操作数（A，B）的N位模加法器功能的比特结果，后跟饱和至M位。 进一步描述执行所述方法的电子计算电路（1,5）。 另外，描述了包括这种电子计算电路的计算机系统。

公开(公告)号：US20100057825A1

公开(公告)日：2010-03-04

申请号：US12028889

申请日：2008-02-11

申请人： Tobias Gemmeke ,  Nicolas Maeding ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Nicolas Maeding ,  Jochen Preiss

IPC分类号： G06F7/50

CPC分类号： G06F7/727 ,  G06F7/499

摘要： A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.

摘要翻译： 描述了一种操作数宽度减小的方法，其中处理位宽N为N的两个N位输入操作数（A，B），并减少位宽M的M位输出操作数（A'，B'） 以一种方式产生，包括在所述两个M位输出操作数（A'，B'）上执行的对M位进行饱和后的M位加法器功能的后处理提供等于M的M位结果 两个N位输入操作数（A，B）的N位模加法器功能的比特结果，后跟饱和至M位。 进一步描述执行所述方法的电子计算电路（1,5）。 另外，描述了包括这种电子计算电路的计算机系统。

公开(公告)号：US08452824B2

公开(公告)日：2013-05-28

申请号：US11872846

申请日：2007-10-16

申请人： Tobias Gemmeke ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jochen Preiss

IPC分类号： G06F15/00

CPC分类号： H03K19/20 ,  G06F7/00 ,  G06F9/30029

摘要： A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.

摘要翻译： 描述了对两个输入信号（va，vb）应用任何布尔运算的二进制逻辑单元，其中要施加到输入信号（va，vb）上的任何布尔运算由明确定​​义的控制信号（ct10 ，ctl1，ctl2，ctl3），其中输入信号（va，vb）用于选择控制信号（ctl0，ctl1，ctl2，ctl3）作为代表a的结果的二进制逻辑单元的输出信号（vo） 特定的布尔运算应用于两个输入信号（va，vb）。 此外，描述了操作这种二进制逻辑单元的方法。

公开(公告)号：US07639046B2

公开(公告)日：2009-12-29

申请号：US11850736

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： H03K19/00 ,  H03K17/16 ,  H03K19/003 ,  G06F1/00 ,  G05F1/10 ,  G05F3/02

CPC分类号： H03K19/0016

摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

摘要翻译： 一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活 来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播 每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号 通过时钟门控同步电路。

公开(公告)号：US20080169842A1

公开(公告)日：2008-07-17

申请号：US11850745

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.

摘要翻译： 一种用于降低时钟门控同步电路内的功耗的设计结构，所述同步电路包括至少两个连续级，其中每个级如果被激活，则逐周期地将数据信号周期传播到后级，所述两个连续级包括至少一个控制寄存器 ，数据寄存器和本地时钟缓冲器（LCB），其中每个级如果被激活，则将周期内存储的数据信号周期传播到后级的数据寄存器。

公开(公告)号：US20080169841A1

公开(公告)日：2008-07-17

申请号：US11850736

申请日：2007-09-06

申请人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

发明人： Tobias Gemmeke ,  Jens Leenstra ,  Jochen Preiss

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

摘要翻译： 一种降低时钟门控同步电路内的功耗的方法，所述同步电路包括至少两个连续的级，其中每个阶段如果被激活，则将周期性的数据信号周期传播到后一级，包括以下步骤：导出本地时钟激活 来自外部时钟激活信号的信号，其中所述本地时钟激活信号每周期改变其值，外部时钟激活信号指示传播，数据信号和本地时钟激活信号从一个特定阶段到后一个周期循环传播 每当通过从时钟激活信号导出或通过传播通过同步电路在特定阶段的本地时钟激活信号在两个连续周期之间改变其值时，为了在同一时钟域内传播数据信号和本地时钟激活信号 通过时钟门控同步电路。