公开(公告)号：US06844750B2

公开(公告)日：2005-01-18

申请号：US10401792

申请日：2003-03-31

申请人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

发明人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

IPC分类号： G01R31/30 ,  G11C29/50 ,  G01R31/02

CPC分类号： G11C29/50 ,  G01R31/3012 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.

摘要翻译： 电流镜多通道泄漏监控电路和方法测量管芯泄漏，并产生数字保持器控制位以控制过程补偿动态电路。 泄漏监测器可在芯片上的多个位置进行高分辨率片上泄漏测量，从而节省测试时间，并使裸片和裸片工艺补偿均可实现。

公开(公告)号：US06781892B2

公开(公告)日：2004-08-24

申请号：US10033337

申请日：2001-12-26

申请人： Steven K. Hsu ,  Sanu K. Mathew ,  Ram Krishnamurthy

发明人： Steven K. Hsu ,  Sanu K. Mathew ,  Ram Krishnamurthy

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： A single-ended, full-swing dynamic cache having memory cells grouped into memory groups, where for each memory group one or more foot transistors connect to various memory cells within the memory group. Using a foot transistor reduces sub-threshold leakage current when the memory cells connected to the foot transistor are not being read.

摘要翻译： 具有分组到存储器组中的存储器单元的单端，全摆幅动态高速缓存，其中对于每个存储器组，一个或多个脚晶体管连接到存储器组内的各种存储器单元。 当连接到脚晶体管的存储单元未被读取时，使用脚晶体管可以减小子阈值漏电流。

公开(公告)号：US06618316B2

公开(公告)日：2003-09-09

申请号：US10027414

申请日：2001-12-20

申请人： Steven K. Hsu ,  Ram Krishnamurthy

发明人： Steven K. Hsu ,  Ram Krishnamurthy

IPC分类号： G11C800

CPC分类号： G11C15/04

摘要： A cache memory cell comprising a read-access transistor to access the cell, where the read-access transistor is reverse biased when the memory cell is not being read to reduce sub-threshold leakage current.

摘要翻译： 一种高速缓冲存储器单元，包括用于存取单元的读取存取晶体管，其中当存储单元未被读取时，读取存取晶体管被反向偏置以减小子阈值泄漏电流。

公开(公告)号：US10825509B2

公开(公告)日：2020-11-03

申请号：US16146932

申请日：2018-09-28

申请人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

发明人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C27/02 ,  G11C7/10 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418

摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

公开(公告)号：US20190057050A1

公开(公告)日：2019-02-21

申请号：US16160952

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC分类号： G06F13/16 ,  G06F13/28

摘要： Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US20070299902A1

公开(公告)日：2007-12-27

申请号：US11475704

申请日：2006-06-26

申请人： Mahesh K. Kumashikar ,  Sanu Mathew ,  Ram Krishnamurthy ,  Daniel Jackson

发明人： Mahesh K. Kumashikar ,  Sanu Mathew ,  Ram Krishnamurthy ,  Daniel Jackson

IPC分类号： G06F7/52

CPC分类号： G06F7/508

摘要： Embodiments disclosed herein provide sparse adder circuits comprising Ling type propagate and generate circuits and sparse carry circuits to efficiently add first and second operands to one another.

摘要翻译： 本文公开的实施例提供稀疏加法器电路，其包括Ling型传播并产生电路和稀疏传送电路以有效地将第一和第二操作数彼此添加。

公开(公告)号：US20070233772A1

公开(公告)日：2007-10-04

申请号：US11393392

申请日：2006-03-30

申请人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

发明人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

IPC分类号： G06F7/52

CPC分类号： G06F7/728 ,  G06F7/722

摘要： A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1. Multiplying the least-significant bit of X and bits 2w-1:w of Y may occur at least partially contemporaneously with multiplying the least-significant bit of X and the least-significant w bits of Y, determining if the least-significant bit of product Z is 1, and adding the least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1.

摘要翻译： 处理乘法器X和被乘数Y的系统可以包括X的最低有效位和Y的最低有效位W的乘法以产生乘积Z的最低有效w位。系统还可以包括确定是否 如果产品Z的最低有效位为1，乘积Z的最低有效位为1，则将乘积Z的最低有效位加上最低有效W位的模M， 并且产生Z的位2 w-1：w，并将模数M的位2 w-1：w相加到乘积Z的位2 w-1：w，如果 乘积Z的最低有效位为1.乘以X的最低有效位和Y的位2 w-1：w可以至少部分同时与X的最低有效位乘以最小有效位W 确定产品Z的最低有效位是否为1，并将模数M的最低有效W位加到第 如果产品Z的最低有效位为1，则产品Z的最低有效w位。

公开(公告)号：US07154300B2

公开(公告)日：2006-12-26

申请号：US10744084

申请日：2003-12-24

申请人： Mark A. Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

发明人： Mark A. Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

IPC分类号： H03K19/0175 ,  G06F13/00 ,  G11C7/00

CPC分类号： H04L25/0278 ,  H04L25/028

摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

摘要翻译： 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

公开(公告)号：US07131055B2

公开(公告)日：2006-10-31

申请号：US10372121

申请日：2003-02-25

申请人： Sanu K. Mathew ,  Ram Krishnamurthy ,  Hoang Q. Dao

发明人： Sanu K. Mathew ,  Ram Krishnamurthy ,  Hoang Q. Dao

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/4107

摘要： A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.

摘要翻译： 维特比解码器包括对每个符号周期执行状态度量更新的ACS单元。 状态度量更新涉及将对应于可能的输入符号的状态量度相加到相应的分支矩阵，比较添加的结果以确定哪个更小，并为下一状态度量选择较小的结果。 ACS单元包括两个并行加法器，其后是并行比较器，其产生多路选择器选择信号。 并行加法器的输出被输入到多路复用器中，并且多路复用器选择信号被输入到多路复用器中用于决定。

公开(公告)号：US20060013035A1

公开(公告)日：2006-01-19

申请号：US10879090

申请日：2004-06-30

申请人： Steven Hsu ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Ram Krishnamurthy

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the word-line inverter is local to each cell or sub-cell, DC offset is substantially reduced which translates into a reduction in leakage current.

摘要翻译： 存储器电路包括字线，包括一个或多个存储器单元或子单元的数据存储电路，以及耦合在字线和N个存储单元之间的反相器。 逆变器将输入到单元或子单元的读取端口的字线信号反相。 由于字线逆变器对于每个单元或子单元是局部的，所以DC偏移显着减小，这转化为泄漏电流的减小。