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11.发明授权公开(公告)号：US06707318B2
公开(公告)日：2004-03-16
申请号：US10107740
申请日：2002-03-26
申请人： Sudarshan Kumar , Shahram Jamshidi
发明人： Sudarshan Kumar , Shahram Jamshidi
IPC分类号： H03K19096
CPC分类号： H03K3/356173 , H03K3/012 , H03K19/0963
摘要： An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.
摘要翻译： 输入锁存器，用于响应于下拉网络处的输入静态信号在输出端口处提供动态信号，所述下拉网络根据输入的静态信号来有条件地排放内部节点，所述输入锁存器包括具有第一源的传输晶体管 /漏极连接到输出端口，第二个源极/漏极连接到上拉pMOSFET的栅极，其中只有在评估阶段下拉网络未导通时，上拉电阻pOSOSFET才会导通。
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12.发明授权
公开(公告)号：US6124737A
公开(公告)日：2000-09-26
申请号：US345972
申请日：1999-06-30
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.
摘要翻译： 时钟缓冲器包括时钟上拉晶体管和时钟控制下拉晶体管。 时钟上拉晶体管具有耦合到输出线的漏极和耦合到时钟信号线的栅极。 时钟控制的下拉晶体管包括耦合到输出线的漏极，耦合到时钟信号线的栅极并具有宽度Y.该缓冲器还包括第一下拉晶体管，其具有耦合到时钟信号源的漏极 下拉晶体管，耦合到第一输入信号线的栅极，并且具有比Y大至少10％的宽度。与较传统的时钟缓冲器相比，该时钟缓冲器提供了降低的功耗。
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公开(公告)号：US5579254A
公开(公告)日：1996-11-26
申请号：US471287
申请日：1995-06-06
申请人： Sudarshan Kumar , Jashojiban Banik
发明人： Sudarshan Kumar , Jashojiban Banik
摘要： An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.
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公开(公告)号：US20120057135A1
公开(公告)日：2012-03-08
申请号：US12801468
申请日：2010-09-07
申请人： Sudarshan Kumar
发明人： Sudarshan Kumar
IPC分类号： G03B21/14
CPC分类号： H04N9/3111
摘要： A system comprising of low cost and low power projection engine comprising of means of producing non-coherent light source, means of condensing non-coherent light into narrow beams, means of focusing and scanning narrow beam light on screen where as image is projected on screen by producing light for each pixel of image. Source of non-coherent light can be LED.
摘要翻译： 一种包括低成本和低功率投影引擎的系统，包括产生非相干光源的装置，将非相干光聚焦成窄光束的装置，在屏幕上聚焦和扫描窄光束的装置，其中图像被投影在屏幕上 通过为图像的每个像素产生光。 非相干光源可以是LED。
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公开(公告)号：US6058403A
公开(公告)日：2000-05-02
申请号：US130379
申请日：1998-08-06
IPC分类号： H03K19/096 , G06F7/74 , G06F7/00
CPC分类号： G06F7/74
摘要： A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.
摘要翻译： 一种破碎的堆叠多米诺骨牌优先编码器，用于提供一组电压以唯一地识别二进制字中的前导或前导零的位置，多米诺骨牌优先级编码器包括nMOSFET的旁路堆叠和破坏的nMOSFET堆叠，以排放各种 节点。 为了最大化优先编码器的切换速度，使每个节点和地之间的nMOSFET的堆叠深度最小化。
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公开(公告)号：US5608741A
公开(公告)日：1997-03-04
申请号：US156427
申请日：1993-11-23
申请人： Sudarshan Kumar , Shyue L. Kuo , Chung Y. Yip
发明人： Sudarshan Kumar , Shyue L. Kuo , Chung Y. Yip
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.
摘要翻译： 本发明公开了一种使用使用补码传输晶体管逻辑实现的4位XOR单元的快速奇偶校验位发生器。 对于22n个输入，其中n是任意正整数，奇偶校验位仅使用
4位XOR单元在n个阶段中生成。 对于22n + 1输入，其中n是任意的正整数，使用放置在最后一行中的n行和一个2位XOR单元中的 4位XOR单元产生奇偶校验位。 通过在XOR单元内使用NMOS晶体管逻辑来进一步增强XOR单元的工作速度。 -
公开(公告)号：US5581497A
公开(公告)日：1996-12-03
申请号：US325777
申请日：1994-10-17
申请人： Sudarshan Kumar
发明人： Sudarshan Kumar
CPC分类号： G06F7/506
摘要： An adder is described. The adder generates a block generate signal after one domino gate delay. The adder can also generate a carry out signal, generate a first plurality of sum signals in response to the carry out signal, generate a block generate signal, generate a group generate signal, and generate a second plurality of sum signals in response to the carry out signal, block generate signal and group generate signal.
摘要翻译： 描述加法器。 加法器在一个多米诺门延迟后产生一个块生成信号。 加法器还可以生成进位信号，响应于进位信号产生第一多个和信号，产生块产生信号，产生组生成信号，并响应于进位产生第二多个和信号 输出信号，块生成信号和组生成信号。
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公开(公告)号：US20220013154A1
公开(公告)日：2022-01-13
申请号：US17327602
申请日：2021-05-21
申请人： Sudarshan Kumar
发明人： Sudarshan Kumar
摘要： An integrated circuit might comprise an input flip-flop block clocked by a first clock having a first clock period, an output of the input flip-flop block for outputting data clocked by the first clock, a first logic block implementing a desired logic function, an input of the first logic block, coupled to the input flip-flop block, an output flip-flop block clocked by a second clock having a period equal to the first clock period and derived from a common source as the first clock, and an input of the output flip-flop block, coupled to an output of the first logic block. A first logic block delay can be at least the first clock period plus a specified delay excess and the second clock can be delayed by at least the specified delay excess. The first logic block might be a portion of a CAM block and/or a TCAM block.
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公开(公告)号：US06266757B1
公开(公告)日：2001-07-24
申请号：US09074019
申请日：1998-05-06
申请人： Mehul Desai , Sudarshan Kumar
发明人： Mehul Desai , Sudarshan Kumar
IPC分类号： G06F1206
CPC分类号： G06F7/509 , G06F7/607 , G06F9/355 , G06F9/3555
摘要： A circuit for adding two or more numbers and generating a sum and carry output is disclosed. The adder circuit receives two or more numbers to be added together. The adder circuit includes a number of exclusive-or logic circuits that generate intermediate outputs. The intermediate outputs are input to a domino multiplexer. The domino multiplexer includes a multiplexer gate and an exclusive-or gate connected in parallel. The domino multiplexer circuit outputs a sum value and a carry value for the input numbers. A clock signal drives the multiplexer gate and the exclusive-or gate in the domino multiplexer circuit. This clock signal synchronizes the input of the numbers to be added together and the addition operation in the domino multiplexer circuit.
摘要翻译： 公开了一种用于添加两个或多个数字并产生和和携带输出的电路。 加法器电路接收两个或多个要相加的数字。 加法器电路包括产生中间输出的多个异或逻辑电路。 中间输出输入到多米诺骨牌多路复用器。 多米诺骨牌多路复用器包括多路复用器门和并联连接的异或门。 多米诺骨牌多路复用器电路输出输入号码的和值和进位值。 时钟信号驱动复用器门和多米诺多路复用器电路中的异或门。 该时钟信号将要加到一起的数字的输入和多米诺多路复用器电路中的相加操作同步。
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公开(公告)号：US6127850A
公开(公告)日：2000-10-03
申请号：US346108
申请日：1999-06-30
IPC分类号： H03K19/173 , H03K19/096
CPC分类号： H03K19/1731
摘要： A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.
摘要翻译： 第一上拉晶体管具有耦合到时钟信号线的栅极和耦合到第一下拉晶体管和电压钳两者的漏极。 第二上拉晶体管具有也耦合到时钟信号线的栅极和耦合到第二下拉晶体管和电压钳两者的漏极。 共享下拉晶体管具有也耦合到时钟信号线的栅极和耦合到第一和第二下拉晶体管的漏极。 该电路可用于时钟缓冲应用。
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