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公开(公告)号：US08780657B2
公开(公告)日：2014-07-15
申请号：US13409399
申请日：2012-03-01
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C7/06 , G11C11/41 , G11C29/12 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.
摘要翻译： 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。
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公开(公告)号：US08780654B2
公开(公告)日：2014-07-15
申请号：US13443170
申请日：2012-04-10
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/12 , G11C11/41 , G11C11/419 , G11C29/12015 , G11C29/50
摘要： Embodiments of a memory are disclosed that may allow for the detection and compensation of weak data storage cells. The memory may include data storage cells, a selection circuit, a sense amplifier, and a timing and control block. The timing and control block may be operable to controllably select differing time periods between the activation of the selection circuit and the activation of the sense amplifier.
摘要翻译： 公开了可以允许弱数据存储单元的检测和补偿的存储器的实施例。 存储器可以包括数据存储单元，选择电路，读出放大器以及定时和控制块。 定时和控制块可操作以可控地选择激活选择电路和感测放大器的激活之间的不同时间段。
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公开(公告)号：US08555121B2
公开(公告)日：2013-10-08
申请号：US13026892
申请日：2011-02-14
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/318541 , G01R31/318594
摘要： A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The dynamic node may then drive output device(s). When the evaluate pulse is deasserted, the dynamic node may be precharged. The gate may also include scan input devices, which, during a scan mode of operation, may load scan input data onto the output node in response to assertion of a scan master clock. A storage element of the gate may receive and capture a value of the output node in response to assertion of a slave scan clock.
摘要翻译： 可扫描脉冲动态逻辑门可以包括评估网络，其评估响应于评估脉冲的断言的动态输入。 评估脉冲可以从时钟信号产生，使得其持续时间比时钟信号短。 在正常操作模式期间，当评估脉冲被断言时，评估网络可以根据动态输入的状态来放电动态节点。 然后动态节点可以驱动输出设备。 当评估脉冲无效时，可以对动态节点进行预充电。 门还可以包括扫描输入设备，其在扫描操作模式期间可以响应于扫描主时钟的断言将扫描输入数据加载到输出节点上。 响应于从属扫描时钟的断言，门的存储元件可以接收并捕获输出节点的值。
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公开(公告)号：US08482333B2
公开(公告)日：2013-07-09
申请号：US13274662
申请日：2011-10-17
IPC分类号： H03K3/01
CPC分类号： H03K5/08
摘要： A system and method for reducing power consumption within clock distribution on a semiconductor chip. A 4-phase clock generator within a clock distribution network provides 4 non-overlapping clock signals dependent upon a received input clock. A reduced voltage swing clock generator receives the non-overlapping clock signals and charges and discharges a second set of clock lines in a manner sequenced by the non-overlapping clock signals. The sequencing prevents a voltage range from reaching a magnitude equal to a power supply voltage for each of the second set of clock lines. In one embodiment, the magnitude reaches half of the power supply voltage. The reduced voltage swing latch receives the second set of clock lines. The reduced voltage swing latch updates and maintains logical state based at least upon the received second set of clock lines.
摘要翻译： 一种用于在半导体芯片上降低时钟分布内的功耗的系统和方法。 时钟分配网络内的4相时钟发生器根据接收到的输入时钟提供4个不重叠的时钟信号。 降低电压摆动时钟发生器接收不重叠的时钟信号，并以由非重叠时钟信号排序的方式对第二组时钟线进行充电和放电。 该顺序可防止电压范围达到等于第二组时钟线中的每一个的电源电压的幅度。 在一个实施例中，幅度达到电源电压的一半。 减小的电压摆动锁存器接收第二组时钟线。 至少基于所接收的第二组时钟线，减小的电压摆动锁存器更新并保持逻辑状态。
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15.发明授权Circuits, systems and methods for controlling substrate bias in integrated circuits 失效用于控制集成电路中的衬底偏置的电路，系统和方法
公开(公告)号：US5612644A
公开(公告)日：1997-03-18
申请号：US521891
申请日：1995-08-31
申请人： Michael E. Runas
发明人： Michael E. Runas
IPC分类号： G11C11/407 , G11C5/02 , G11C5/14 , G11C11/4074 , G05F1/10
CPC分类号： G11C5/025 , G11C11/4074 , G11C5/146
摘要： Substrate bias control circuitry 100 is provided which includes a bias sensor 101 for measuring a bias voltage of a substrate and generating a control signal and response. A master oscillator 102 is provided for generating a first driving signal, a frequency of the first driving signal adjusted by the control signal generated by the bias sensor 101. A first charge pump 103 is provided for pumping electrons into a substrate in response to the first driving signal. A slave oscillator generates a second driving signal, a frequency of the second driving signal is determined from the frequency of the first driving signal using a phase-locked loop. A second charge pump 105 is provided for pumping electrons into the substrate in response to the second driving signal.
摘要翻译： 提供了衬底偏置控制电路100，其包括用于测量衬底的偏置电压并产生控制信号和响应的偏置传感器101。 提供主振荡器102，用于产生第一驱动信号，由通过偏置传感器101产生的控制信号调节的第一驱动信号的频率。第一电荷泵103用于响应于第一驱动信号 驾驶信号。 从振荡器产生第二驱动信号，使用锁相环从第一驱动信号的频率确定第二驱动信号的频率。 提供第二电荷泵105以响应于第二驱动信号将电子泵送到衬底中。
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16.发明授权Circuits systems and methods for reducing power loss during transfer of data across a conductive line 失效用于在传输线路中传输数据时减少功率损耗的电路系统和方法
公开(公告)号：US5585744A
公开(公告)日：1996-12-17
申请号：US543210
申请日：1995-10-13
申请人： Michael E. Runas , Ronald T. Taylor
发明人： Michael E. Runas , Ronald T. Taylor
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A line driver 202 is provided for transmitting signals across a line 201. Line driver 202 receives an input signal having a first voltage swing between a first high voltage level and a first low voltage level. Line driver 202 reduces power dissipation in line 201 by transmitting an output signal on line 201 having a second voltage swing between a second low voltage level greater than the first low voltage level and a second high voltage level less than the first high voltage level.
摘要翻译： 线驱动器202被提供用于沿线201传输信号。线驱动器202接收具有在第一高电压电平和第一低电压电平之间的第一电压摆幅的输入信号。 线路驱动器202通过在线路201上传输具有大于第一低电压电平的第二低电压电平和小于第一高电压电平的第二高电压电平之间的第二电压摆幅的输出信号来减少线路201中的功率消耗。
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公开(公告)号：US09177671B2
公开(公告)日：2015-11-03
申请号：US13403543
申请日：2012-02-23
CPC分类号： G11C29/50 , G11C11/41 , G11C29/52 , G11C2029/5002
摘要： A memory that may allow for the detection of weak data storage cells may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.
摘要翻译： 可能允许检测弱数据存储单元的存储器可以包括数据存储单元，列多路复用器，读出放大器和负载电路。 负载电路可以包括一个或多个容性负载，并且可操作以可控制地选择一个或多个容性负载以耦合到读出放大器的输入端。
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公开(公告)号：US08677199B2
公开(公告)日：2014-03-18
申请号：US13026878
申请日：2011-02-14
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/318541 , G01R31/318594
摘要： A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The resultant state of the dynamic node may be stored within an output storage element. When the evaluate pulse is deasserted, the dynamic node may be precharged. During a scan mode of operation, the dynamic node may remain precharged. Scan data may be transferred to the output storage element under the control of scan-related control signals.
摘要翻译： 可扫描脉冲动态逻辑门可以包括评估网络，其评估响应于评估脉冲的断言的动态输入。 评估脉冲可以从时钟信号产生，使得其持续时间比时钟信号短。 在正常操作模式期间，当评估脉冲被断言时，评估网络可以根据动态输入的状态来放电动态节点。 动态节点的合成状态可以存储在输出存储元件内。 当评估脉冲无效时，可以对动态节点进行预充电。 在扫描操作模式期间，动态节点可以保持预充电。 扫描数据可以在扫描相关控制信号的控制下传送到输出存储元件。
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公开(公告)号：US5663984A
公开(公告)日：1997-09-02
申请号：US434656
申请日：1995-05-04
申请人： Michael E. Runas
发明人： Michael E. Runas
CPC分类号： H04L25/0272 , H04L25/028 , H04L25/0292
摘要： Circuitry 200 is provided for transmitting data between a first endpoint and a second endpoint and includes an information line 201 and a dummy line 205. Information transmission circuitry 202, 203, 204 is disposed at the first endpoint for transmitting information on information line 201, transmission circuitry 202, 203, 204 pulling information line 201 to a low voltage during transmission of information of a first logic state and charging information line 201 to a higher voltage during transmission of information of a second logic state. Charging circuitry 206, 207, 208 is disposed at the first endpoint for charging dummy line 205 to a reference voltage during transmission of information on information line 201, charging circuitry 206, 207, 208 charging dummy line 205 at a rate different from a rate at which transmission circuitry 202, 203, 204 charges information line 201 during transmission of information of the second logic state. Receiving circuitry 209 is disposed at the second endpoint for detecting a voltage difference between information line 201 and dummy line 205 and in response determining the logic state of transmitted data on information line 201.
摘要翻译： 提供电路200用于在第一端点和第二端点之间传输数据，并且包括信息线201和虚线205.信息传输电路202,203,204设置在用于在信息线201上发送信息的第一端点，传输 电路202,203,204在第二逻辑状态的信息的传输期间将信息线路201向第一逻辑状态和充电信息线路201的信息传输到更高的电压期间将信号线201拉到低电压。 充电电路206,207,208设置在第一端点处，用于在信息线路201上充电虚拟线路205的信号到充电虚拟线路205的信息，充电电路206,207,208以不同于 哪个传输电路202,203,204在传输第二逻辑状态的信息期间对信息线路201进行收费。 接收电路209设置在第二端点处，用于检测信息线201和虚拟线路205之间的电压差，并且响应于确定信息线路201上发送的数据的逻辑状态。
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20.发明授权
公开(公告)号：US5592077A
公开(公告)日：1997-01-07
申请号：US387218
申请日：1995-02-13
申请人： Michael E. Runas , Kirit B. Patel
发明人： Michael E. Runas , Kirit B. Patel
CPC分类号： G11C29/021 , G01R31/3004 , G11C29/02 , G11C29/50 , G11C2029/5004 , G11C2029/5006
摘要： Systems and methods for testing ASIC and RAM memory devices are disclosed. The method comprises determining a signature map of valid power supply current values for a known good microcircuit wherein each valid power supply current value is measured at a fixed level of power supply voltage and corresponds to a unique test input stimuli pattern applied to the known good microcircuit. The signature map of power supply current values is stored in an electronic memory (300). The test input stimuli patterns are then applied to an unproven microcircuit (330) and the power supply current of the unproven microcircuit is forced to the levels stored in the signature map by a current supply (360) while the voltages across the power supply inputs of the unproven microcircuit are measured by a voltmeter (340). The measured power supply voltages for each power supply current value are then compared to the fixed voltage supply level used to test the known good microcircuit. The unproven microcircuit is faulted if any measured power supply voltage of the unproven microcircuit differs substantially from the fixed power supply voltage applied to the known good microcircuit.
摘要翻译： 公开了用于测试ASIC和RAM存储器件的系统和方法。 该方法包括确定用于已知良好微电路的有效电源电流值的签名图，其中每个有效电源电流值以固定电源电压水平测量并对应于应用于已知的良好微电路的唯一测试输入刺激模式 。 电源电流值的签名图存储在电子存储器（300）中。 然后将测试输入刺激模式应用于未验证的微电路（330），并且将未验证的微电路的电源电流通过电流供应（360）强制到存储在签名图中的电平，同时电源输入端 未经证实的微电路由电压表（340）测量。 然后将每个电源电流值的测量电源电压与用于测试已知的良好微电路的固定电压电平进行比较。 如果未验证的微电路的任何测量的电源电压与施加到已知的良好微型电路的固定电源电压显着不同，则未经证实的微电路故障。
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