公开(公告)号：US5815675A

公开(公告)日：1998-09-29

申请号：US670273

申请日：1996-06-13

Applicant: James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

Inventor： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F13/161 ,  G06F12/0835

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract translation: 一种计算机系统，其中主机总线从主存储器和连接到输入/输出（I / O）总线的设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 因此，由于主机总线可用于其他处理操作，而不是与连接到I / O总线的设备（例如，外围设备）进行数据传输相结合，因此计算机系统具有显着更好的性能。

公开(公告)号：US5761454A

公开(公告)日：1998-06-02

申请号：US703563

申请日：1996-08-27

Applicant: Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

Inventor： Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

IPC: G06F13/42 ,  G06F13/36

CPC classification number: G06F13/4226

Abstract: A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit. There is further included second circuit for determining whether the PCI slave is still able to complete the PCI-MEMORY transaction. Additionally, there is included third circuit for asserting an asynchronous handshake acknowledge signal to cancel the CPU-PCI transaction and removing the deadlock condition if the PCI slave is unable to complete the PCI-MEMORY transaction.

Abstract translation: 一种用于解决耦合到计算机系统的存储器，主机总线和PCI总线的桥式电路中的死锁状态的死锁检测和分辨率电路。 主机总线和PCI总线被配置为同时和异步地运行。 桥接电路包括主机主电路和耦合在主机总线和PCI总线之间的PCI从属电路，并配置为从耦合到PCI总线的外部PCI主机服务PCI-MEMORY指令。 桥接电路内的PCI主电路和主机从电路耦合在PCI总线和主机总线之间，并配置为从耦合到主机总线的CPU服务CPU-PCI事务。 当PCI-MEMORY事务随着CPU-PCI事务的发布而同时进行时，发生上述死锁条件。 死锁检测和分辨率电路包括用于向桥接电路的PCI从站断言异步握手信号的第一电路。 还包括用于确定PCI从站是否仍然能够完成PCI-MEMORY事务的第二电路。 另外，包括用于断言异步握手确认信号以消除CPU-PCI事务的第三电路，并且如果PCI从设备不能完成PCI-MEMORY事务，则消除死锁条件。

公开(公告)号：US06543018B1

公开(公告)日：2003-04-01

申请号：US09454244

申请日：1999-12-02

Applicant: Swaroop Adusumilli ,  Manoj Chandran

Inventor： Swaroop Adusumilli ,  Manoj Chandran

IPC: G01R3128

CPC classification number: G01R31/318547

Abstract: The present invention is a system and method that facilitates flexible restriction of output transmissions from chosen scan test cells and reduces adverse impacts on functional components from coincidental test vector values during scan test operations. The system and method of the present invention provides the capability of masking test vector values that coincidentally trigger certain undesirable events in functional components. In one embodiment, a system and method of the present invention masks test vector values shifted into scan test cells that are coupled to bus driver enabling signals. The system and method of the of the present invention also facilitates flexible selection of which scan test cell outputs are masked and permits a scan test cell to provide a scan test vector value to an associated functional component and prevent coincidental transmission of inappropriate test vector values.

Abstract translation: 本发明是一种系统和方法，其有助于灵活地限制来自所选择的扫描测试单元的输出传输，并且在扫描测试操作期间减少对巧合测试向量值对功能组件的不利影响。 本发明的系统和方法提供了屏蔽测试向量值的能力，其巧妙地触发功能组件中的某些不良事件。 在一个实施例中，本发明的系统和方法掩盖移入耦合到总线驱动使能信号的扫描测试单元的测试向量值。 本发明的系统和方法还有助于灵活地选择哪个扫描测试单元输出被屏蔽，并允许扫描测试单元向相关联的功能组件提供扫描测试向量值，并防止错误的测试矢量值的巧合传输。

公开(公告)号：US06418545B1

公开(公告)日：2002-07-09

申请号：US09326492

申请日：1999-06-04

Applicant: Swaroop Adusumilli

Inventor： Swaroop Adusumilli

IPC: G01R3128

CPC classification number: G01R31/318555

Abstract: The present invention is a system and method that permits appropriate scan testing of internal components of an integrated circuit while reducing the number of external pins required to perform the scan testing. One embodiment of the present invention utilizes standard IEEE 1149.1 pins (e.g. TDO, TDI, TMS, TCK, etc.) to perform both boundary scan and full scan testing. A modified IEEE 1149.1 TAP controller generates signals to control the boundary scan and full scan operations. For example, a full scan cell facilitates full scan capture and shift operations when the TAP controller generates a full scan test mode signal and a full scan enable signal in response to inputs via the standard IEEE 1149.1 pins. In one example the scan enable signal is asserted when the TAP controller is in a shift state and the TAP controller's instruction register is loaded with a test mode instruction. A functional clock capture cycle is applied when the state machine of the TAP controller is in run/idle state.

Abstract translation: 本发明是一种系统和方法，其允许对集成电路的内部组件进行适当的扫描测试，同时减少执行扫描测试所需的外部引脚的数量。 本发明的一个实施例使用标准IEEE 1149.1引脚（例如TDO，TDI，TMS，TCK等）来执行边界扫描和全扫描测试。 经修改的IEEE 1149.1 TAP控制器产生信号以控制边界扫描和全扫描操作。 例如，当TAP控制器响应于通过标准IEEE 1149.1引脚的输入产生全扫描测试模式信号和全扫描使能信号时，全扫描单元便于全扫描捕获和移位操作。 在一个示例中，当TAP控制器处于移位状态并且TAP控制器的指令寄存器被加载了测试模式指令时，扫描使能信号被置位。 当TAP控制器的状态机处于运行/空闲状态时，应用功能时钟捕获周期。

公开(公告)号：US06412030B1

公开(公告)日：2002-06-25

申请号：US09293077

申请日：1999-04-16

Applicant: Swaroop Adusumilli

Inventor： Swaroop Adusumilli

IPC: G06F1328

CPC classification number: G06F13/1621

Abstract: The present invention is a system and method that minimizes discarding of a pending read transaction in a peripheral component interconnect (PCI) bus architecture due to an arrival of a write request while maintaining appropriate transaction ordering. The read/write optimizing system and method of the present invention optimizes read performance by continuing to process a pending read transaction under appropriate conditions while partially performing the write request and inhibiting its completion. In one embodiment of the read/write optimizing system and method of the present invention, a write transaction is inhibited by tracking or storing an inhibited write transaction target address if a pending read transaction address is not within a range of an inhibited write transaction address. For example, a target address associated with an inhibited write transaction is temporarily latched in a write address register until a pending read transaction is completed or terminated. During the same time frame the inhibited write transaction is also partially processed by latching write data in a target write buffer if a target is prepared and a pending read transaction address does not come within a range of an inhibited write transaction address as the pending read and inhibited write transactions are processed.

Abstract translation: 本发明是一种系统和方法，其最小化由于在写入请求的到达而保持适当的事务排序的情况下，在外围组件互连（PCI）总线架构中丢弃待处理的读取事务。 本发明的读/写优化系统和方法通过在适当的条件下继续处理待处理的读取事务来优化读取性能，同时部分执行写入请求并阻止其完成。 在本发明的读/写优化系统和方法的一个实施例中，如果挂起的读事务地址不在禁止的写事务地址的范围内，则通过跟踪或存储禁止的写事务目标地址来禁止写事务。 例如，与被禁止的写入事务相关联的目标地址被暂时锁存在写入地址寄存器中，直到等待读取事务完成或终止为止。 在同一时间帧期间，如果准备了目标并且待处理的读取事务地址不在禁止的写入事务地址的范围内作为未决读取，则通过将写入数据锁定在目标写入缓冲器中而被部分地处理， 禁止写入事务处理。

公开(公告)号：US5793992A

公开(公告)日：1998-08-11

申请号：US664107

申请日：1996-06-13

Applicant: James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

Inventor： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/00 ,  G06F13/362

CPC classification number: G06F13/1605 ,  G06F13/4027 ,  G06F13/4031

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

Abstract translation: 一种计算机系统，其中主机总线从连接到输入/输出（I / O）总线（例如，外围设备）的主存储器和设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 此外，为了减少寻求通过主机总线和内部总线访问主存储器的处理器的停止，主总线能够在暂时不需要内部总线的时间期间使用内部总线来访问主存储器 通过主存储器和外围设备之间的数据传输。 因此，由于主机总线可用于其他处理操作，而不是与外围设备的数据传输相关联，因此内部总线在主存储器之间的数据传输期间偶尔被释放，因此计算机系统具有显着更好的性能 和外围设备。