公开(公告)号：US20070262016A1

公开(公告)日：2007-11-15

申请号：US11770834

申请日：2007-06-29

Applicant: Brian Fall ,  Thomas Hamlin ,  Mahesh Patel ,  John Pulek ,  Aaron Spearin

Inventor： Brian Fall ,  Thomas Hamlin ,  Mahesh Patel ,  John Pulek ,  Aaron Spearin

IPC: B01D29/07 ,  B01D39/00

CPC classification number: B01D29/111 ,  B01D29/21 ,  B01D29/232 ,  B01D29/54 ,  B01D2201/122 ,  Y10T156/1025 ,  Y10T156/1038 ,  Y10T156/1051

Abstract: A filter assembly is provided which includes an outer filter sleeve formed at least in part by a plurality of pleats, an inner filter sleeve formed at least in part by a plurality of pleats, wherein the inner and outer filter sleeves define a passage therebetween. An inlet cap is secured to a first end of the inner and outer filter sleeves and it has at least one inlet port communicating with the passage, and an end cap is secured to a second end of the inner and outer filter sleeves and it has an end surface closing the passage. Methods of forming such a filter assembly are also provided.

Abstract translation: 提供了一种过滤器组件，其包括至少部分地由多个褶皱形成的外部过滤器套筒，至少部分地由多个褶皱形成的内部过滤器套筒，其中内部和外部过滤器套筒在其间限定通道。 入口盖固定到内过滤器套筒和外过滤器套筒的第一端，并且其具有与通道连通的至少一个入口端口，并且端盖固定到内过滤器套筒和外过滤套筒的第二端，并且其具有 端面关闭通道。 还提供了形成这种过滤器组件的方法。

公开(公告)号：US5815675A

公开(公告)日：1998-09-29

申请号：US670273

申请日：1996-06-13

Applicant: James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

Inventor： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F13/161 ,  G06F12/0835

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract translation: 一种计算机系统，其中主机总线从主存储器和连接到输入/输出（I / O）总线的设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 因此，由于主机总线可用于其他处理操作，而不是与连接到I / O总线的设备（例如，外围设备）进行数据传输相结合，因此计算机系统具有显着更好的性能。

公开(公告)号：US20050166036A1

公开(公告)日：2005-07-28

申请号：US10969338

申请日：2004-10-19

Applicant: Michael Catherwood ,  Edward Boles ,  Stephen Bowling ,  Joshua Conner ,  Rodney Drake ,  John Elliott ,  Brian Fall ,  James Grosbach ,  Tracy Kuhrt ,  Guy McCarthy ,  Manuel Muro ,  Mike Pyska ,  Joseph Triece

Inventor： Michael Catherwood ,  Edward Boles ,  Stephen Bowling ,  Joshua Conner ,  Rodney Drake ,  John Elliott ,  Brian Fall ,  James Grosbach ,  Tracy Kuhrt ,  Guy McCarthy ,  Manuel Muro ,  Mike Pyska ,  Joseph Triece

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F15/00

CPC classification number: G06F9/3885 ,  G06F9/30014 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/325 ,  G06F9/3893

Abstract: An instruction set is provided that features multiple instructions and various address modes to deliver a mixture of flexible microcontroller-like instructions and specialized digital signal processing (“DSP”) execute instructions from a single instruction stream. A subset of instructions of the instruction set can be executed by a processor. Similarly, another subset of the instructions can be utilized by the digital signal processor. A software application can thus take advantage of digital signal processing capabilities in the same program, obviating the need for separate programs for separate processors.

Abstract translation: 提供了一种指令集，其具有多个指令和各种地址模式，以提供灵活的类似微控制器的指令和专用数字信号处理（“DSP”）的混合从单个指令流执行指令。 指令集的指令子集可由处理器执行。 类似地，数字信号处理器可以利用指令的另一子集。 因此，软件应用程序可以利用同一程序中的数字信号处理能力，从而避免对单独处理器的单独程序的需要。

公开(公告)号：US20060108277A1

公开(公告)日：2006-05-25

申请号：US10993824

申请日：2004-11-19

Applicant: Brian Fall ,  Thomas Hamlin ,  Mahesh Patel ,  John Pulek ,  Aaron Spearin

Inventor： Brian Fall ,  Thomas Hamlin ,  Mahesh Patel ,  John Pulek ,  Aaron Spearin

IPC: B01D29/07

CPC classification number: B01D29/111 ,  B01D29/21 ,  B01D29/232 ,  B01D29/54 ,  B01D2201/122 ,  Y10T156/1025 ,  Y10T156/1038 ,  Y10T156/1051

Abstract: A filter assembly is provided which includes an outer filter sleeve formed at least in part by a plurality of pleats, an inner filter sleeve formed at least in part by a plurality of pleats, wherein the inner and outer filter sleeves define a passage therebetween. An inlet cap is secured to a first end of the inner and outer filter sleeves and it has at least one inlet port communicating with the passage, and an end cap is secured to a second end of the inner and outer filter sleeves and it has an end surface closing the passage. Methods of forming such a filter assembly are also provided.

Abstract translation: 提供了一种过滤器组件，其包括至少部分地由多个褶皱形成的外部过滤器套筒，至少部分地由多个褶皱形成的内部过滤器套筒，其中内部和外部过滤器套筒在其间限定通道。 入口盖固定到内过滤器套筒和外过滤器套筒的第一端，并且其具有与通道连通的至少一个入口端口，并且端盖固定到内过滤器套筒和外过滤套筒的第二端，并且其具有 端面关闭通道。 还提供了形成这种过滤器组件的方法。

公开(公告)号：US5793992A

公开(公告)日：1998-08-11

申请号：US664107

申请日：1996-06-13

Applicant: James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

Inventor： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/00 ,  G06F13/362

CPC classification number: G06F13/1605 ,  G06F13/4027 ,  G06F13/4031

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

Abstract translation: 一种计算机系统，其中主机总线从连接到输入/输出（I / O）总线（例如，外围设备）的主存储器和设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 此外，为了减少寻求通过主机总线和内部总线访问主存储器的处理器的停止，主总线能够在暂时不需要内部总线的时间期间使用内部总线来访问主存储器 通过主存储器和外围设备之间的数据传输。 因此，由于主机总线可用于其他处理操作，而不是与外围设备的数据传输相关联，因此内部总线在主存储器之间的数据传输期间偶尔被释放，因此计算机系统具有显着更好的性能 和外围设备。