公开(公告)号：US5793992A

公开(公告)日：1998-08-11

申请号：US664107

申请日：1996-06-13

申请人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

发明人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/00 ,  G06F13/362

CPC分类号： G06F13/1605 ,  G06F13/4027 ,  G06F13/4031

摘要： A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

摘要翻译： 一种计算机系统，其中主机总线从连接到输入/输出（I / O）总线（例如，外围设备）的主存储器和设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 此外，为了减少寻求通过主机总线和内部总线访问主存储器的处理器的停止，主总线能够在暂时不需要内部总线的时间期间使用内部总线来访问主存储器 通过主存储器和外围设备之间的数据传输。 因此，由于主机总线可用于其他处理操作，而不是与外围设备的数据传输相关联，因此内部总线在主存储器之间的数据传输期间偶尔被释放，因此计算机系统具有显着更好的性能 和外围设备。

公开(公告)号：US5815675A

公开(公告)日：1998-09-29

申请号：US670273

申请日：1996-06-13

申请人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

发明人： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC分类号： G06F12/08 ,  G06F13/16

CPC分类号： G06F13/161 ,  G06F12/0835

摘要： A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

摘要翻译： 一种计算机系统，其中主机总线从主存储器和连接到输入/输出（I / O）总线的设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 因此，由于主机总线可用于其他处理操作，而不是与连接到I / O总线的设备（例如，外围设备）进行数据传输相结合，因此计算机系统具有显着更好的性能。

公开(公告)号：US5761454A

公开(公告)日：1998-06-02

申请号：US703563

申请日：1996-08-27

申请人： Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

发明人： Swaroop Adusumilli ,  Barry M. Davis ,  Brian N. Fall ,  Nicholas J. Richardson ,  Philip Wszolek

IPC分类号： G06F13/42 ,  G06F13/36

CPC分类号： G06F13/4226

摘要： A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are configured to operate concurrently and asynchronously. The bridge circuit includes a host master circuit and a PCI slave circuit coupled between the host bus and the PCI bus and configured to service a PCI-MEMORY instruction from an external PCI master coupled to the PCI bus. A PCI master circuit and a host slave circuit within the bridge circuit couples between the PCI bus and the host bus and configured to service a CPU-PCI transaction from a CPU coupled to the host bus. The aforementioned deadlock condition occurs when the PCI-MEMORY transaction proceeds simultaneous with an issuance of the CPU-PCI transaction. The deadlock detection and resolution circuit includes first circuit for asserting an asynchronous handshake signal to the PCI slave of the bridge circuit. There is further included second circuit for determining whether the PCI slave is still able to complete the PCI-MEMORY transaction. Additionally, there is included third circuit for asserting an asynchronous handshake acknowledge signal to cancel the CPU-PCI transaction and removing the deadlock condition if the PCI slave is unable to complete the PCI-MEMORY transaction.

摘要翻译： 一种用于解决耦合到计算机系统的存储器，主机总线和PCI总线的桥式电路中的死锁状态的死锁检测和分辨率电路。 主机总线和PCI总线被配置为同时和异步地运行。 桥接电路包括主机主电路和耦合在主机总线和PCI总线之间的PCI从属电路，并配置为从耦合到PCI总线的外部PCI主机服务PCI-MEMORY指令。 桥接电路内的PCI主电路和主机从电路耦合在PCI总线和主机总线之间，并配置为从耦合到主机总线的CPU服务CPU-PCI事务。 当PCI-MEMORY事务随着CPU-PCI事务的发布而同时进行时，发生上述死锁条件。 死锁检测和分辨率电路包括用于向桥接电路的PCI从站断言异步握手信号的第一电路。 还包括用于确定PCI从站是否仍然能够完成PCI-MEMORY事务的第二电路。 另外，包括用于断言异步握手确认信号以消除CPU-PCI事务的第三电路，并且如果PCI从设备不能完成PCI-MEMORY事务，则消除死锁条件。

公开(公告)号：US5737544A

公开(公告)日：1998-04-07

申请号：US628969

申请日：1996-04-08

申请人： Philip Wszolek

发明人： Philip Wszolek

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/423

摘要： A link system controller is interposed between a PCI bus and the CPU data bus and memory data bus of a personal computer system to ensure that the transfer of data from the PCI bus to the CPU data bus occurs on different clock signals from the transfer of data from the PCI bus to the memory data bus. This is accomplished by an authorizing circuit, which alternately enables a CPU bus interface controller and a memory data bus controller in response to alternating clock signals. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise below an acceptable threshold; so that the operation of the IC system device is not impaired.

摘要翻译： 一个链路系统控制器被插在一个PCI总线和个人计算机系统的CPU数据总线和存储器数据总线之间，以确保数据从PCI总线传输到CPU数据总线上发生在与数据传输不同的时钟信号上 从PCI总线到存储器数据总线。 这是通过授权电路实现的，该电路可交替地使CPU总线接口控制器和存储器数据总线控制器响应于交替的时钟信号。 这防止CPU数据总线和存储器数据总线上的设备的同时切换，以将噪声的产生降低到可接受的阈值以下; 使得IC系统设备的操作不受损害。

公开(公告)号：US5737545A

公开(公告)日：1998-04-07

申请号：US651698

申请日：1996-05-21

申请人： Philip Wszolek ,  Barry Martin Davis ,  Brian Neil Fall ,  Richard Demers

发明人： Philip Wszolek ,  Barry Martin Davis ,  Brian Neil Fall ,  Richard Demers

IPC分类号： G06F13/362 ,  H01J13/00

CPC分类号： G06F13/362

摘要： A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.

摘要翻译： 一种方法和系统被设计为通过总线主控或者也包括PCI总线的系统中的直接存储器访问设备来保证ISA总线的可用性。 这通过将PCI总线上的锁定通过桥接器件到PCI配置空间寄存器的配置读取来实现。 锁定建立后，防止其他PCI设备锁定PCI总线上的任何其他资源。 PCI配置空间存在于ISA驻留设备可以生成访问的存储器或I / O范围之外。 因此，每当ISA驻留设备生成其访问时，它都是已知不处于锁定状态的设备。 因此，总线交易能够在ISA驻留设备预期的期限内完成。

公开(公告)号：US5732226A

公开(公告)日：1998-03-24

申请号：US629011

申请日：1996-04-08

申请人： Philip Wszolek ,  Rodney James Pesavento ,  Brian Neil Fall ,  James Crawford Steele

发明人： Philip Wszolek ,  Rodney James Pesavento ,  Brian Neil Fall ,  James Crawford Steele

IPC分类号： G06F13/16 ,  G06F13/36

CPC分类号： G06F13/1605 ,  Y02B60/1228

摘要： A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.

摘要翻译： 链路系统控制器被插入在PCI总线与个人计算机系统的数据总线和存储器数据总线之间，以正常允许将写入信息从PCI总线传送到存储器数据总线上的DRAM存储器。 每当要求将数据传送到CPU数据总线时，CPU总线接口控制器要求从DRAM控制器释放系统。 只要DRAM控制器不将数据写入DRAM数据总线，DRAM控制器就可以向CPU总线接口授予许可或释放控制权。 当该释放被实现时，防止将写入数据传送到存储器数据总线，并且能够将数据传送到CPU数据总线。 这防止了CPU数据总线和存储器数据总线上的设备的同时切换，以减少噪声的产生; 使得IC系统设备的操作不受损害。

公开(公告)号：US5724613A

公开(公告)日：1998-03-03

申请号：US643350

申请日：1996-05-06

申请人： Philip Wszolek

发明人： Philip Wszolek

IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0215 ,  G06F13/1631

摘要： The present invention relates to a system and method which has automatic enabling and disabling capabilities for prefetching and transferring sequentially located data from system memory to a First In First Out (FIFO) queue. When a Peripheral Component Interconnect (PCI) initiator signals for a data read, a minimum unit of data will be transferred from system memory to the FIFO queue. Only after seeing a certain number of consecutive data read requests from the same PCI initiator will the system begin to sequentially prefetch data from system memory and to transfer the prefetched data to the FIFO queue.

摘要翻译： 本发明涉及一种具有自动启用和禁用功能的系统和方法，用于将从系统存储器顺序定位的数据预取和传送到先进先出（FIFO）队列。 外设组件互连（PCI）启动器为数据读取器发送信号时，数据的最小单位将从系统存储器传送到FIFO队列。 只有在从同一个PCI启动器看到一定数量的连续数据读取请求之后，系统将开始从系统存储器中顺序地预取数据并将预取的数据传送到FIFO队列。

公开(公告)号：US5752262A

公开(公告)日：1998-05-12

申请号：US687242

申请日：1996-07-25

申请人： David K. Cassetti ,  Philip Wszolek

发明人： David K. Cassetti ,  Philip Wszolek

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0811

摘要： A cache memory system operates without requiring valid bits in the external cache tag RAM by employing a system controller as a writeback cache controller for control of the cache data/tag memory and the system main memory. The system controller receives signaling information from a CPU through a host bus to indicate when to pre-load the cache memory or to flush (disable) the cache memory while maintaining memory coherencey by causing the cache controller to write back all modified lines in the cache memory to the main memory.

摘要翻译： 高速缓冲存储器系统通过采用系统控制器作为用于控制高速缓存数据/标签存储器和系统主存储器的回写高速缓存控制器，而不需要外部高速缓存标签RAM中的有效位进行操作。 系统控制器通过主机总线从CPU接收信令信息，以指示何时预加载高速缓冲存储器，或通过使高速缓存控制器回写高速缓存中的所有修改行来维护存储器一致性来刷新（禁用）高速缓冲存储器 内存到主内存。