公开(公告)号：US5817567A

公开(公告)日：1998-10-06

申请号：US826710

申请日：1997-04-07

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches are then filled with a conformal layer of silicon oxide. This is followed by overcoating with a layer of a hard material such as silicon nitride or boron nitride. Next, chemical-mechanical polishing is used to remove the hard layer everywhere except where it has filled the depressions that overlie the trenches. Then, a non-selective etch is used to remove the remaining hard layer material as well as some of the silicon oxide, so that a planar surface is maintained. Finally, chemical-mechanical polishing is used a second time to remove excess silicon oxide from above the trenches' surface.

摘要翻译： 描述了一种用于在集成电路中实现浅沟槽隔离的改进方法。 该方法开始于通过图案化和蚀刻形成沟槽。 然后用保形层的氧化硅填充这些沟槽。 随后用一层硬质材料如氮化硅或氮化硼涂覆。 接下来，使用化学机械抛光来去除硬质层，除了填充了覆盖在沟槽上的凹陷之外。 然后，使用非选择性蚀刻来除去剩余的硬质层材料以​​及一些氧化硅，从而保持平坦的表面。 最后，第二次使用化学机械抛光从沟槽表面上方除去过量的氧化硅。

公开(公告)号：US5741740A

公开(公告)日：1998-04-21

申请号：US873836

申请日：1997-06-12

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/76224 ,  Y10S148/05

摘要： A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then formed upon the thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material. To provide improved properties of the gap filling silicon oxide trench fill layer the thermal silicon oxide trench liner layer may be treated with a nitrogen containing plasma prior to forming the conformal silicon oxide intermediate layer thereupon.

摘要翻译： 一种用于在硅衬底内填充沟槽的方法。 首先提供其中形成有沟槽的硅衬底。 然后将硅衬底热氧化以在沟槽内形成热氧化硅沟槽衬垫层。 然后在热氧化硅沟槽衬垫层上形成通过使用硅烷硅源材料的等离子体增强化学气相沉积（PECVD）方法形成的共形氧化硅中间层。 最后，通过使用臭氧氧化剂和四乙基原硅酸盐的臭氧辅助亚大气压热化学气相沉积（SACVD）方法，在保形氧化硅中间层上形成填充氧化硅沟槽填充层的间隙 （TEOS）硅源材料。 为了提供间隙填充氧化硅沟槽填充层的改进性能，可以在形成其之间的共形氧化硅中间层之前用含氮等离子体处理热氧化硅沟槽衬里层。

公开(公告)号：US06239002B1

公开(公告)日：2001-05-29

申请号：US09174660

申请日：1998-10-19

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76205

摘要： A method for forming a trench isolation region within a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then formed over the silicon substrate and filling the trench a silicon oxide trench fill layer. There is then thermally oxidized the silicon substrate and the silicon oxide trench fill layer within a thermal oxidation atmosphere to form a densified silicon oxide trench fill layer upon a silicon oxide trench liner layer within an oxidized trench within an oxidized silicon substrate, where the silicon oxide trench liner layer is formed from oxidation of the silicon substrate when forming the oxidized silicon substrate.

摘要翻译： 一种用于在硅衬底内的沟槽内形成沟槽隔离区的方法。 首先提供其中形成有沟槽的硅衬底。 然后形成在硅衬底上并且将沟槽填充到氧化硅沟槽填充层。 然后在热氧化气氛中热氧化硅衬底和氧化硅沟槽填充层，以在氧化硅衬底内的氧化沟槽内的氧化硅沟槽衬垫层上形成致密的氧化硅沟槽填充层，其中氧化硅 当形成氧化硅衬底时，沟槽衬垫层由硅衬底的氧化形成。

公开(公告)号：US06171896B2

公开(公告)日：2001-01-09

申请号：US08794597

申请日：1997-02-03

申请人： Syun-Ming Jang ,  Chen-Hua Yu ,  Ying-Ho Chen

发明人： Syun-Ming Jang ,  Chen-Hua Yu ,  Ying-Ho Chen

IPC分类号： H01L218238

CPC分类号： H01L21/76229

摘要： A method for forming planarized shallow trench isolation is described. A pad oxide layer is grown over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches are etched through the nitride and pad oxide layers into the semiconductor substrate wherein there are at least one first wide nitride region between two of the trenches and at least one second narrow nitride region between another two of the trenches. A high density plasma oxide layer is deposited over the nitride layer and within the isolation trenches wherein the high density plasma oxide layer fills the isolation trenches and wherein the high density plasma oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer. A photoresist mask is formed over the high density plasma oxide layer. The substrate is exposed to actinic light wherein a central portion of the first region is exposed. The high density plasma oxide layer is etched away where it has been exposed. The high density plasma oxide layer remaining is polished away whereby the substrate is planarized and fabrication of said integrated circuit device is completed.

摘要翻译： 描述了形成平坦化浅沟槽隔离的方法。 衬底氧化物层生长在半导体衬底的表面上。 在衬垫氧化物层上沉积氮化物层。 通过氮化物和衬垫氧化物层蚀刻多个隔离沟槽到半导体衬底中，其中在两个沟槽之间存在至少一个第一宽氮化物区域和另外两个沟槽之间的至少一个第二窄氮化物区域。 高密度等离子体氧化物层沉积在氮化物层之上和隔离沟槽内，其中高密度等离子体氧化物层填充隔离沟槽，并且其中高密度等离子体氧化物在宽氮化物层上的第一区域中更厚地沉积并沉积更多 在窄的氮化物层上的第二区域中薄。 在高密度等离子体氧化物层上形成光刻胶掩模。 将基板暴露于其中暴露第一区域的中心部分的光化光。 将高密度等离子体氧化物层蚀刻掉已被暴露的地方。 抛光剩余的高密度等离子体氧化物层，由此使衬底平坦化，并且完成所述集成电路器件的制造。

公开(公告)号：US5869384A

公开(公告)日：1999-02-09

申请号：US820467

申请日：1997-03-17

申请人： Chen-Hua Yu ,  Syun-Ming Jang ,  Ying-Ho Chen

发明人： Chen-Hua Yu ,  Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for filling a trench within a substrate. There is first provided a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a silicon layer. The silicon layer has an aperture formed therein where the silicon layer is formed within the trench. There is then formed upon the silicon layer and filling the aperture a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) method. Finally, the substrate is annealed thermally in an oxygen containing atmosphere to form within the trench an oxidized silicon layer from the silicon layer, where the oxidized silicon layer is contiguous with a densified gap filling silicon oxide trench fill layer simultaneously formed from the gap filling silicon oxide trench fill layer. Through the method, the densified gap filling silicon oxide trench fill layer is formed without a surface sensitivity.

摘要翻译： 一种填充衬底内的沟槽的方法。 首先提供在衬底内形成沟槽的衬底。 然后形成在衬底上并且在沟槽内形成硅层。 硅层在其中形成有孔，其中硅层形成在沟槽内。 然后在硅层上形成填充孔的填充氧化硅沟槽填充层的间隙。 通过臭氧辅助亚大气压化学气相沉积（SACVD）方法形成填充氧化硅沟槽填充层的间隙。 最后，将衬底在含氧气氛中进行热退火以在沟槽内形成来自硅层的氧化硅层，其中氧化硅层与填充氧化硅沟槽填充层的致密化间隙连续，同时由间隙填充硅 氧化物沟填充层。 通过该方法，形成密集的间隙填充氧化硅沟槽填充层，而不具有表面灵敏度。

公开(公告)号：US5731241A

公开(公告)日：1998-03-24

申请号：US857160

申请日：1997-05-15

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O.sub.3 TEOS layer 50 70 over a trench oxide 40 to protect the trench oxide from excessive subsequent etch steps. The SACVD O.sub.3 TEOS layer has a higher deposition rate over the trench oxide layer 40 than over the surrounding non-trench thermally grown pad oxides. The trench oxide is preferably formed using a process of PECVD, LPTEOS, or O.sub.3 -TEOS. The invention provides two preferred embodiments: (1) a first self aligned sacrificial O.sub.3 TEOS oxide layer 50 deposited before the pad oxide etch and (2) a second self aligned sacrificial O.sub.3 TEOS oxide layer 70 deposited before the sacrificial implant oxide etch. The invention can be applied in a variety of situations where the trench oxide is exposed to damaging etches.

摘要翻译： 本发明提供了一种在沟槽氧化物40上制造牺牲自对准亚大气压化学气相沉积（SACVD）O3 TEOS层5070的方法，以保护沟槽氧化物免于过多的后续蚀刻步骤。 SACVD O3 TEOS层在沟槽氧化物层40上的沉积速率高于周围的非沟槽热生长焊盘氧化物。 沟槽氧化物优选使用PECVD，LPTEOS或O3-TEOS的工艺形成。 本发明提供了两个优选实施例：（1）在氧化层蚀刻之前沉积的第一自对准牺牲O 3 TEOS氧化物层50和（2）在牺牲注入氧化物蚀刻之前沉积的第二自对准牺牲O 3 TEOS氧化物层70。 本发明可以应用于各种情况，其中沟槽氧化物暴露于有害蚀刻。

公开(公告)号：US5702977A

公开(公告)日：1997-12-30

申请号：US810390

申请日：1997-03-03

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer. The trench fill layer is formed to a thickness over the trench such that when the trench fill layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill layer formed within the trench.

摘要翻译： 一种在集成电路内的衬底内的沟槽内形成平坦化沟槽填充层的方法。 首先提供其中形成有沟槽的衬底。 在沟槽内的不同于沟槽内的区域的基底上形成第一集成电路层，该第一集成电路层具有阻止在沟槽填充层的第一集成电路层上形成的组成，后者形成在衬底上并在沟槽内。 在沟槽内还形成在衬底上的不在沟槽内的衬底上的第二集成电路层，该第二集成电路层具有促进在沟槽填充层的沟槽内形成的组成，其随后形成在衬底上并在衬底内 沟。 最后，在衬底上并在沟槽内形成沟槽填充层。 沟槽填充层形成为在沟槽上方的厚度，使得当沟槽填充层通过化学机械抛光（CMP）平面化方法平坦化时，避免在形成在沟槽内的平坦化沟槽填充层内形成皿。

公开(公告)号：US6143673A

公开(公告)日：2000-11-07

申请号：US409888

申请日：1999-10-01

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Shwangming Jeng ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Shwangming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/31

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/31116 ,  H01L21/31612

摘要： A method for forming within a microelectronics fabrication a dielectric layer formed over, around and between patterned conductor layers. There is first provided a substrate employed within a microelectronics fabrication upon which is formed a patterned conductor layers. There is then formed over the patterned conductor layer a silicon oxide dielectric layer. There is then treated the silicon oxide dielectric layer to an anisotropic sputter etching process to remove silicon oxide dielectric material without re-deposition from the bottom of the gap between lines of the patterned conductor layer and to reform the silicon oxide dielectric layers on the sidewalls of the patterned lines to form spacer layers thereon. Both the silicon oxide dielectric layer deposition process and the sputter etching process may be repeated as desired to form the desired depth of trench and shape of spacer layer. There is then exposed the substrate to a nitrogen plasma. There is then formed over the substrate a gap filling silicon oxide dielectric layer to complete the formation of the inter-level dielectric layer with minimal void content in gaps between patterned lines.

摘要翻译： 在微电子制造中形成在图案化导体层之上，周围和之间形成介电层的方法。 首先提供在微电子制造中使用的衬底，其上形成图案化的导体层。 然后在图案化的导体层上形成氧化硅介电层。 然后将氧化硅介电层处理成各向异性溅射蚀刻工艺以去除氧化硅介电材料，而不从图案化导体层的线之间的间隙的底部重新沉积，并且重新形成在图案化导体层的侧壁上的氧化硅介电层 图案化线以在其上形成间隔层。 可以根据需要重复氧化硅介电层沉积工艺和溅射蚀刻工艺，以形成期望的沟槽深度和间隔层的形状。 然后将基板暴露于氮等离子体。 然后在衬底上形成填充氧化硅介电层的间隙，以在图案化线之间的间隙中以最小的空隙含量完成层间电介质层的形成。

公开(公告)号：US06049137A

公开(公告)日：2000-04-11

申请号：US106331

申请日：1998-06-29

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chung-Long Chang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chung-Long Chang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/102 ,  Y10S438/975

摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.

摘要翻译： 可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。 提供了包括产品区域12和对准标记区域30的半导体衬底10。 对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方 绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

公开(公告)号：US6043136A

公开(公告)日：2000-03-28

申请号：US121710

申请日：1998-07-24

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A method for forming a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a silicon oxide layer, where the silicon oxide layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1. Finally, there is then annealed thermally the substrate within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the silicon oxide layer a densified silicon oxide layer. The densified silicon oxide layer formed employing the method is formed with an unexpectedly low shrinkage.

摘要翻译： 一种形成氧化硅层的方法。 首先提供基板。 然后在衬底上形成氧化硅层，其中通过使用臭氧氧化剂和四乙基原硅酸盐（TEOS）的臭氧辅助亚大气压力热化学气相沉积（SACVD）方法形成氧化硅层 ）硅源材料：TEOS体积比为约10:1至约14:1。 最后，在含氧气氛中，在大于约1100摄氏度的温度下将衬底热处理，从氧化硅层形成致密氧化硅层。 使用该方法形成的致密氧化硅层形成意想不到的低收缩率。