公开(公告)号：US20210320072A1

公开(公告)日：2021-10-14

申请号：US17356039

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu LEE ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US11037920B2

公开(公告)日：2021-06-15

申请号：US16744975

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Jung-Chan Yang ,  Lee-Chung Lu ,  Po-Hsiang Huang ,  Chun-Chen Chen

IPC: H01L27/02 ,  H01L27/118 ,  G06F30/394 ,  G06F30/392

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US10964685B2

公开(公告)日：2021-03-30

申请号：US16724001

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

Abstract: An integrated circuit includes a cell layer, a first metal layer, a first conductive via, and a second conductive via. The cell layer includes first and second cells, in which the first cell is separated from the second cell by a non-zero distance. The first metal layer includes a first conductive feature and a second conductive feature, the first conductive feature overlaps the first cell and does not overlap the second cell, and the second conductive feature overlaps the second cell and does not overlap the first cell, in which the first conductive feature is aligned with the second conductive feature along lengthwise directions of the first and second conductive features. The first conductive via interconnects the cell layer and the first conductive feature of the first metal layer. The second conductive via interconnects the cell layer and the second conductive feature of the first metal layer.

公开(公告)号：US20200089840A1

公开(公告)日：2020-03-19

申请号：US16690578

申请日：2019-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Huan WANG ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Po-Hsiang Huang

IPC: G06F17/50 ,  G03F1/36

Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.

公开(公告)号：US20200020644A1

公开(公告)日：2020-01-16

申请号：US16043355

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu LEE ,  Chin-Chou Liu ,  Cheng-Hung Yeh ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Ka Fai Chang

IPC: H01L23/552 ,  H01L49/02 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.

公开(公告)号：US10521545B2

公开(公告)日：2019-12-31

申请号：US15099780

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Huan Wang ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Po-Hsiang Huang

IPC: G06F17/50 ,  G03F1/36

Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.

公开(公告)号：US20190064770A1

公开(公告)日：2019-02-28

申请号：US15800693

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung CHEN ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Shao-Huan Wang ,  XinYong Wang ,  Yi-Kan Cheng ,  Chun-Chen Chen

IPC: G05B19/4097 ,  G06F17/50 ,  H01L27/02

Abstract: Exemplary embodiments for multiple standard cell libraries are disclosed that include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations have similar functionality as their one or more standard cells but are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for analog circuitry and/or digital circuitry of an electronic device. In an exemplary embodiment, a semiconductor foundry and/or semiconductor technology node can impose one or more electronic design constraints on the placement of the one or more standard cells onto an electronic device design real estate. In some situations, some of the one or more standard cells are unable to satisfy the one or more electronic design constraints when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

公开(公告)号：US20240379541A1

公开(公告)日：2024-11-14

申请号：US18784823

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Lee ,  Po-Hsiang Huang ,  Wen-Sheh Huang ,  Jen Hung Wang ,  Su-Jen Sung ,  Chih-Chien Chi ,  Pei-Hsuan Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

公开(公告)号：US12056432B2

公开(公告)日：2024-08-06

申请号：US18300142

申请日：2023-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chun-Chen Chen ,  Sheng-Hsiung Chen ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Jung-Chan Yang ,  Lee-Chung Lu ,  Po-Hsiang Huang

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US12027513B2

公开(公告)日：2024-07-02

申请号：US18224434

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Po-Hsiang Huang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Ka Fai CHang

IPC: H01L25/065 ,  G11C8/18 ,  H01L23/48 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0207 ,  G11C8/18 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/0688

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.