公开(公告)号：US12154842B2

公开(公告)日：2024-11-26

申请号：US18347013

申请日：2023-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsiang Huang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Fong-yuan Chang ,  Hui Yu Lee

IPC: H01L23/42 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US11923302B2

公开(公告)日：2024-03-05

申请号：US17854683

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Noor Mohamed Ettuveettil ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/08135 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08147

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

公开(公告)号：US20230057672A1

公开(公告)日：2023-02-23

申请号：US17981274

申请日：2022-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jul Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  G06F30/398 ,  H01L27/02

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

公开(公告)号：US11585831B2

公开(公告)日：2023-02-21

申请号：US16995866

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC: G01R1/07 ,  G01R1/073

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US11094608B2

公开(公告)日：2021-08-17

申请号：US16433967

申请日：2019-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Hsiang Huang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Fong-yuan Chang ,  Hui Yu Lee

IPC: H01L23/42 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

公开(公告)号：US10943729B2

公开(公告)日：2021-03-09

申请号：US16456025

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ka Fai Chang ,  Chin-Chou Liu ,  Fong-Yuan Chang ,  Hui Yu Lee ,  Yi-Kan Cheng

IPC: H01L27/08 ,  H01F27/34 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

公开(公告)号：US20200379013A1

公开(公告)日：2020-12-03

申请号：US16995866

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC: G01R1/073

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US10782318B2

公开(公告)日：2020-09-22

申请号：US15789338

申请日：2017-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC: G01R1/073

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US10163708B2

公开(公告)日：2018-12-25

申请号：US15710368

申请日：2017-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jr Huang ,  William Wu Shen ,  Chin-Her Chien ,  Chin-Chou Liu ,  Yun-Han Lee

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48 ,  H01Q9/04 ,  H01L23/00 ,  H01L23/48

Abstract: Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.

公开(公告)号：US10120971B2

公开(公告)日：2018-11-06

申请号：US15250934

申请日：2016-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lo ,  Chin-Chou Liu ,  Kuo-Nan Yang ,  Yu-Jen Chang

IPC: H01L23/48 ,  G06F17/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.