公开(公告)号：US20240387377A1

公开(公告)日：2024-11-21

申请号：US18788956

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Noor Mohamed Ettuveettil ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

公开(公告)号：US20240371839A1

公开(公告)日：2024-11-07

申请号：US18772438

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Jyh Chwen Frank Lee ,  Yii-Chian Lu ,  Yu-Hao Chen ,  Keh-Jeng Chang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

公开(公告)号：US12074148B2

公开(公告)日：2024-08-27

申请号：US18074027

申请日：2022-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Jyh Chwen Frank Lee ,  Yii-Chian Lu ,  Yu-Hao Chen ,  Keh-Jeng Chang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

公开(公告)号：US20240203997A1

公开(公告)日：2024-06-20

申请号：US18595049

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jui Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  G06F30/398 ,  H01L27/02

CPC classification number: H01L27/11807 ,  G06F30/398 ,  H01L27/0207 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

公开(公告)号：US11901228B2

公开(公告)日：2024-02-13

申请号：US17371416

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cai-Ling Wu ,  Hsiu-Wen Hsueh ,  Wei-Ren Wang ,  Po-Hsiang Huang ,  Chii-Ping Chen ,  Jen Hung Wang

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53295

Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

公开(公告)号：US11586797B2

公开(公告)日：2023-02-21

申请号：US17179904

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Cheng-Hung Yeh ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Yi-Kan Cheng ,  Hsiu-Chuan Shu

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

公开(公告)号：US11527518B2

公开(公告)日：2022-12-13

申请号：US17157520

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Jyh Chwen Frank Lee ,  Yii-Chian Lu ,  Yu-Hao Chen ,  Keh-Jeng Chang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

公开(公告)号：US11410926B2

公开(公告)日：2022-08-09

申请号：US16938450

申请日：2020-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Jiao Fu ,  Po-Hsiang Huang ,  Derek Hsu ,  Hsiu-Wen Hsueh ,  Meng-Sheng Chang

IPC: H01L23/525 ,  H01L23/485 ,  H01L23/00 ,  H01L21/768

Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.

公开(公告)号：US11222884B2

公开(公告)日：2022-01-11

申请号：US16530631

申请日：2019-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Chin-Chou Liu ,  Chin-Her Chien ,  Po-Hsiang Huang ,  Ka Fai Chang

IPC: H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  G11C8/18 ,  H01L23/48

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

公开(公告)号：US11182533B2

公开(公告)日：2021-11-23

申请号：US16912061

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Chen ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Shao-Huan Wang ,  XinYong Wang ,  Yi-Kan Cheng ,  Chun-Chen Chen

IPC: G06F30/00 ,  G06F30/398 ,  H01L27/02 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20 ,  G06F119/18 ,  G06F30/18

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.