公开(公告)号：US12107581B2

公开(公告)日：2024-10-01

申请号：US18362916

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

IPC: H03K3/037 ,  G06F1/12 ,  H03K19/20

CPC classification number: H03K3/037 ,  G06F1/12 ,  H03K19/20

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

公开(公告)号：US12047079B2

公开(公告)日：2024-07-23

申请号：US18302178

申请日：2023-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yung-Chen Chien ,  Xiangdong Chen ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Jerry Chang Jui Kao ,  Lee-Chung Lu

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/0375

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

公开(公告)号：US12039242B2

公开(公告)日：2024-07-16

申请号：US17008067

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Jerry Chang Jui Kao ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Tzu-Ying Lin ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/3953 ,  H01L27/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L27/092

CPC classification number: G06F30/392 ,  G06F30/3953 ,  H01L27/0207 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4238 ,  H01L27/092

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

公开(公告)号：US20240077534A1

公开(公告)日：2024-03-07

申请号：US18150830

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

公开(公告)号：US11870441B2

公开(公告)日：2024-01-09

申请号：US18065327

申请日：2022-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

IPC: H03K3/037 ,  H03K19/20 ,  G06F1/12

CPC classification number: H03K3/037 ,  G06F1/12 ,  H03K19/20

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

公开(公告)号：US12166487B2

公开(公告)日：2024-12-10

申请号：US18152017

申请日：2023-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Huaixin Xian ,  Tzu-Ying Lin ,  Liu Han ,  Jerry Chang Jui Kao ,  Qingchao Meng ,  Xiangdong Chen

IPC: H03K3/037 ,  G01R31/3177 ,  G01R31/3185 ,  H03K19/00 ,  H03K19/0948

Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.

公开(公告)号：US12066489B2

公开(公告)日：2024-08-20

申请号：US18150830

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Johnny Chiahao Li ,  Sheng-Hsiung Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Xiangdong Chen

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318525 ,  G01R31/318541 ,  G01R31/318555

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

公开(公告)号：US20230114367A1

公开(公告)日：2023-04-13

申请号：US18064961

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chien ,  Shao-Lun Chien

IPC: H03K3/037 ,  G01R31/317 ,  G01R31/3177

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

公开(公告)号：US11545965B2

公开(公告)日：2023-01-03

申请号：US17095191

申请日：2020-11-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chen ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

IPC: H03K3/037 ,  G06F1/12 ,  H03K19/20

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

公开(公告)号：US10970451B2

公开(公告)日：2021-04-06

申请号：US16553958

申请日：2019-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jian-Sing Li ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Li-Chun Tien ,  Ting Yu Chen ,  Tzu-Ying Lin

IPC: G06F30/392 ,  H01L27/02

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.