公开(公告)号：US11569168B2

公开(公告)日：2023-01-31

申请号：US17195868

申请日：2021-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei Wu ,  Pochun Wang ,  Wei-Hsin Tsai ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/092

Abstract: An integrated circuit includes a first power rail, a second power rail, a signal line and a first active region of a first set of transistors. The first power rail is on a back-side of a substrate, and extends in a first direction. The second power rail is on the back-side of the substrate, extends in the first direction, and is separated from the first power rail in a second direction different from the first direction. The signal line is on the back-side of the substrate, and extends in the first direction, and is between the first power rail and the second power rail. The first active region of the first set of transistors extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side.

公开(公告)号：US12027598B2

公开(公告)日：2024-07-02

申请号：US17331356

申请日：2021-05-26

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Guo-Huei Wu ,  Pochun Wang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L29/423 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/0673

Abstract: A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.

公开(公告)号：US11508661B2

公开(公告)日：2022-11-22

申请号：US16936249

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu ,  Shih-Ming Chang

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/39 ,  G06F30/392

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

公开(公告)号：US20220384598A1

公开(公告)日：2022-12-01

申请号：US17331356

申请日：2021-05-26

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Guo-Huei Wu ,  Pochun Wang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L29/423 ,  H01L29/06

Abstract: A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.

公开(公告)号：US20190341387A1

公开(公告)日：2019-11-07

申请号：US16515709

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/108 ,  H01L27/02 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US11894383B2

公开(公告)日：2024-02-06

申请号：US17829330

申请日：2022-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  B82Y10/00 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  H01L21/768 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L21/74 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L23/528 ,  H01L23/5226

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

公开(公告)号：US11776958B2

公开(公告)日：2023-10-03

申请号：US17840430

申请日：2022-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Guo-Huei Wu ,  Pochun Wang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/092 ,  G06F30/392 ,  G06F30/31 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  G06F111/02

CPC classification number: H01L27/0922 ,  G06F30/31 ,  G06F30/392 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5286 ,  G06F2111/02

Abstract: A semiconductor device includes a buried communication (com) conductor (BC) CFET including: first and second active regions arranged in a stack according to CFET-type configuration; a first layer of metallization (M_1st layer) over the stack which includes first conductors configured for data or control signals (communication (com) conductors), and power grid (PG) conductors; and a layer of metallization (M_B layer) below the stack and which includes second com conductors.

公开(公告)号：US11550986B2

公开(公告)日：2023-01-10

申请号：US17326811

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Yu-Jung Chang ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang

IPC: G06F30/392 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20 ,  H01L23/522 ,  H01L23/528 ,  G06F30/39

Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.

公开(公告)号：US11048849B2

公开(公告)日：2021-06-29

申请号：US16659270

申请日：2019-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Yu-Jung Chang

IPC: G06F30/392 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20 ,  H01L23/522 ,  H01L23/528 ,  G06F30/39

Abstract: An integrated circuit includes a first active region, a second active region, a third active region, a first contact and a second contact. The first active region and the second active region are separated from each other in a first direction, and are located on a first level. The third active region is located on the first level and is separated from the second active region in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first contact and the third active region, is electrically coupled to the first contact, and is located on a third level different from the first level and the second level.

公开(公告)号：US11004855B2

公开(公告)日：2021-05-11

申请号：US16515709

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.