公开(公告)号：US11082271B2

公开(公告)日：2021-08-03

申请号：US16900010

申请日：2020-06-12

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Abhijit Anant Patki ,  Madhulatha Bonu ,  Kumar Anurag Shrivastava

IPC: H04L27/22 ,  H03D3/00 ,  H03L7/081 ,  H04L27/227 ,  H03K19/21 ,  H03L7/087 ,  H03L7/113 ,  H04L7/033 ,  H04L7/00

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

公开(公告)号：US10797921B2

公开(公告)日：2020-10-06

申请号：US16450065

申请日：2019-06-24

Applicant: Texas Instruments Incorporated

Inventor： Nikolaus Klemmer ,  Amneh Mohammed Akour ,  Abhijit Anant Patki ,  Timothy Patrick Pauletti

IPC: H04L27/14 ,  H04L27/148 ,  H04B1/69

Abstract: A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.

公开(公告)号：US20200259690A1

公开(公告)日：2020-08-13

申请号：US16450065

申请日：2019-06-24

Applicant: Texas Instruments Incorporated

Inventor： Nikolaus Klemmer ,  Amneh Mohammed Akour ,  Abhijit Anant Patki ,  Timothy Patrick Pauletti

IPC: H04L27/148 ,  H04B1/69

Abstract: A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.

公开(公告)号：US20180131545A1

公开(公告)日：2018-05-10

申请号：US15860988

申请日：2018-01-03

Applicant: Texas Instruments Incorporated

Inventor： Subhashish Mukherjee ,  Abhijit Anant Patki ,  Madhulatha Bonu ,  Kumar Anurag Shrivastava

IPC: H04L27/22 ,  H04L7/033 ,  H03K19/21 ,  H03L7/113 ,  H03L7/087 ,  H04L7/00

CPC classification number: H04L27/22 ,  H03D3/00 ,  H03K19/21 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H04L7/0087 ,  H04L7/0331 ,  H04L27/2271

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.