中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

107 records (took 0.021 seconds)

    Third tap circuitry controlling linking first and second tap circuitry
    11.
    发明授权
    Third tap circuitry controlling linking first and second tap circuitry 有权

    公开(公告)号：US09817070B2

    公开(公告)日：2017-11-14

    申请号：US15134877

    申请日：2016-04-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

    IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

    CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    IC test linking module with augmentation instruction shift register
    13.
    发明授权
    IC test linking module with augmentation instruction shift register 有权
    IC测试链接模块与增补指令移位寄存器

    公开(公告)号：US08850279B2

    公开(公告)日：2014-09-30

    申请号：US14190314

    申请日：2014-02-26

    Applicant: Texas Instruments Incorporated

    Inventor： Baher S. Haroun ,  Lee D. Whetsel

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    Abstract translation: 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使得测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

    Shifting instruction data through IRS of IC TAP and TLM
    14.
    发明授权
    Shifting instruction data through IRS of IC TAP and TLM 有权
    通过IC TAP和TLM的IRS转移指令数据

    公开(公告)号：US08726111B2

    公开(公告)日：2014-05-13

    申请号：US13938793

    申请日：2013-07-10

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

    IPC: G01R31/28

    CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    Abstract translation: IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

    Tap and linking module TDO register, gating for TCK and TMS
    15.
    发明授权
    Tap and linking module TDO register, gating for TCK and TMS 有权
    点击和链接模块TDO寄存器，选通TCK和TMS

    公开(公告)号：US08713389B2

    公开(公告)日：2014-04-29

    申请号：US14044535

    申请日：2013-10-02

    Applicant: Texas Instruments Incorporated

    Inventor： Baher S. Haroun ,  Lee D. Whetsel

    IPC: G01R31/28

    CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    Abstract translation: 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使得测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

    Systems and Methods of Tone Management in Hysteretic Mode DC to DC Converter
    16.
    发明申请
    Systems and Methods of Tone Management in Hysteretic Mode DC to DC Converter 有权
    滞后模式DC-DC转换器的音频管理系统与方法

    公开(公告)号：US20140097810A1

    公开(公告)日：2014-04-10

    申请号：US13647156

    申请日：2012-10-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Harikrishna Parthasarathy ,  Srinivas Venkata Veeramreddi ,  Sudhir Polarouthu ,  Baher S. Haroun

    IPC: H02J1/02

    CPC classification number: H02M3/1563

    Abstract: As disclosed herein, two hysteresis levels, a high level a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using a set of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.

    Abstract translation: 如本文所公开的，可以使用两个滞后电平（高电平低电平）来设置DC-DC转换器的输出电压的周期（和开关频率）以及转换器的输出纹波。 这两个阈值可以使用一组开关来改变。 通过控制开关的导通时间的顺序和持续时间，可以控制输出中的频谱杂散，并且可以减小感兴趣的幅度和频带。 通过对开关的控制进行随机化，可以实现额外的齿间减少。

    1149.1 TAP LINKING MODULES
    17.
    发明申请
    1149.1 TAP LINKING MODULES 有权

    公开(公告)号：US20130305108A1

    公开(公告)日：2013-11-14

    申请号：US13938793

    申请日：2013-07-10

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    TSV Testing Using Test Circuits and Grounding Means
    19.
    发明申请
    TSV Testing Using Test Circuits and Grounding Means 有权
    使用测试电路和接地装置进行TSV测试

    公开(公告)号：US20130249590A1

    公开(公告)日：2013-09-26

    申请号：US13785284

    申请日：2013-03-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Baher S. Haroun

    IPC: G01R31/26

    CPC classification number: G01R31/3177 ,  G01R31/26 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318577

    Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

    Abstract translation: 本公开描述了一种用于测试半导体器件内的TSV的新颖方法和装置。 根据本公开中所示和描述的实施例，可以通过刺激和测量来自TSV的第一端的响应来测试TSV，同时TSV的第二端保持在地电位。 根据本公开，可以并行测试半导体器件内的多个TSV以减少TSV测试时间。

    Output linking circuitry for multiple TAP domains
    20.
    发明授权
    Output linking circuitry for multiple TAP domains 有权
    用于多个TAP域的输出链接电路

    公开(公告)号：US08516320B2

    公开(公告)日：2013-08-20

    申请号：US13670078

    申请日：2012-11-06

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

    IPC: G01R31/28

    CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

    Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

    Abstract translation: IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

Patent Agency Ranking