公开(公告)号：US20220328438A1

公开(公告)日：2022-10-13

申请号：US17809854

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Joseph LIU

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US20220155109A1

公开(公告)日：2022-05-19

申请号：US16950981

申请日：2020-11-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan Kalyani KODURI ,  Christopher Daniel MANACK ,  Leslie Edward STARK

IPC: G01D11/24 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: In examples, a sensor package includes a semiconductor die, a sensor on the semiconductor die, and a ring encircling the sensor. The sensor and an inner surface of the ring are exposed to an exterior environment of the sensor package. The sensor package includes a mold compound covering the semiconductor die and abutting an outer surface of the ring.

公开(公告)号：US20220068744A1

公开(公告)日：2022-03-03

申请号：US17003382

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Todd WYANT ,  Matthew John SHERBIN ,  Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  You Chye HOW

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/552 ,  H01L21/56 ,  H01L21/683

Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

公开(公告)号：US20210134750A1

公开(公告)日：2021-05-06

申请号：US16669070

申请日：2019-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel MANACK ,  Salvatore Frank PAVONE ,  Maricel Fabia ESCAÑO ,  Rafael Jose Lizares GUEVARA

IPC: H01L23/00

Abstract: In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.

公开(公告)号：US20200321299A1

公开(公告)日：2020-10-08

申请号：US16909649

申请日：2020-06-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila DADVAND ,  Christopher Daniel MANACK ,  Salvatore Frank PAVONE

IPC: H01L23/00

Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1