公开(公告)号：US20200371934A1

公开(公告)日：2020-11-26

申请号：US16882229

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0817 ,  G06F12/084 ,  G06F12/0811

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

公开(公告)号：US20200371930A1

公开(公告)日：2020-11-26

申请号：US16882216

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/128

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

公开(公告)号：US20200371925A1

公开(公告)日：2020-11-26

申请号：US16882356

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/12 ,  G06F9/30

Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

公开(公告)号：US20200371924A1

公开(公告)日：2020-11-26

申请号：US16882329

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  David Matthew THOMPSON

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F9/30 ,  G06F13/16

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

公开(公告)号：US20200371923A1

公开(公告)日：2020-11-26

申请号：US16882305

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA ,  Peter Michael HIPPLEHEUSER

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/0895 ,  G06F12/0817 ,  G06F9/46 ,  G06F9/54

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

公开(公告)号：US20200371920A1

公开(公告)日：2020-11-26

申请号：US16882202

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Naveen BHORIA

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

公开(公告)号：US20200371919A1

公开(公告)日：2020-11-26

申请号：US16882178

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F9/30 ,  G06F13/16 ,  G06F11/30

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

公开(公告)号：US20250036522A1

公开(公告)日：2025-01-30

申请号：US18915677

申请日：2024-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David Matthew THOMPSON ,  Abhijeet Ashok CHACHAD

IPC: G06F11/10 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0879 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16 ,  H03M13/15

Abstract: A device includes memory blocks; connections respectively coupled to the memory blocks; and control logic coupled to the memory blocks. The control logic is operable to control performance of error-related transactions on the memory blocks via the connections. Such control may include causing a first error-related transaction to be performed on a first memory block of the memory blocks during a first time period, causing a second error-related transaction to be performed on a second memory block of the memory blocks during a second time period, and causing a transaction that is not an error-related transaction to be performed on at least one of the memory blocks, except the first memory block, during performance of one or both of the first error-related transaction and the second error-related transaction.

公开(公告)号：US20250013569A1

公开(公告)日：2025-01-09

申请号：US18894324

申请日：2024-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Timothy David ANDERSON ,  Kai CHIRCA

IPC: G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

公开(公告)号：US20240345868A1

公开(公告)日：2024-10-17

申请号：US18753113

申请日：2024-06-25

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/121 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.